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Fri, 07 Dec 2018 09:58:58 -0800 (PST) Received: from localhost ([216.3.10.7]) by smtp.gmail.com with ESMTPSA id 69sm4707846pgg.86.2018.12.07.09.58.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Dec 2018 09:58:57 -0800 (PST) Date: Fri, 07 Dec 2018 09:58:57 -0800 (PST) X-Google-Original-Date: Fri, 07 Dec 2018 09:58:25 PST (-0800) Subject: Re: [PATCH v2 2/2] clocksource: riscv_timer: Provide sched_clock In-Reply-To: <20181204102952.21297-3-anup@brainfault.org> CC: daniel.lezcano@linaro.org, tglx@linutronix.de, aou@eecs.berkeley.edu, atish.patra@wdc.com, Christoph Hellwig , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, anup@brainfault.org From: Palmer Dabbelt To: anup@brainfault.org Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 04 Dec 2018 02:29:52 PST (-0800), anup@brainfault.org wrote: > Currently, we don't have a sched_clock registered for RISC-V systems. > This means Linux time keeping will use jiffies (running at HZ) as the > default sched_clock. > > To avoid this, we explicity provide sched_clock using RISC-V rdtime > instruction (similar to riscv_timer clocksource). > > Signed-off-by: Anup Patel > --- > drivers/clocksource/Kconfig | 2 +- > drivers/clocksource/riscv_timer.c | 9 +++++++++ > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 55c77e44bb2d..19649abd7c75 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -611,7 +611,7 @@ config ATCPIT100_TIMER > > config RISCV_TIMER > bool "Timer for the RISC-V platform" > - depends on RISCV > + depends on GENERIC_SCHED_CLOCK && RISCV > default y > select TIMER_PROBE > select TIMER_OF > diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c > index 084e97dc10ed..431892200a08 100644 > --- a/drivers/clocksource/riscv_timer.c > +++ b/drivers/clocksource/riscv_timer.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -49,6 +50,11 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) > return get_cycles64(); > } > > +static u64 riscv_sched_clock(void) > +{ > + return get_cycles64(); > +} > + > static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { > .name = "riscv_clocksource", > .rating = 300, > @@ -97,6 +103,9 @@ static int __init riscv_timer_init_dt(struct device_node *n) > cs = per_cpu_ptr(&riscv_clocksource, cpuid); > clocksource_register_hz(cs, riscv_timebase); > > + sched_clock_register(riscv_sched_clock, > + BITS_PER_LONG, riscv_timebase); > + > error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, > "clockevents/riscv/timer:starting", > riscv_timer_starting_cpu, riscv_timer_dying_cpu); Reviewed-by: Palmer Dabbelt