Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <20181127074249.15204-1-icenowy@aosc.io> <20181127074249.15204-2-icenowy@aosc.io>
 <11894938.HOUtrQJeEF@phil>
In-Reply-To: <11894938.HOUtrQJeEF@phil>
From:   Rob Herring <robh+dt@kernel.org>
Date:   Tue, 11 Dec 2018 11:04:59 -0600
Message-ID: <CAL_Jsq+FjW3WEEPkefN_d3K7z=vrz3GfYdWQCY0PHs_+gtAigw@mail.gmail.com>
Subject: Re: [PATCH 2/2] dt-bindings: gpu: add Allwinner H6 Mali Midgard binding
To:     "heiko@sntech.de" <heiko@sntech.de>,
        Neil Armstrong <narmstrong@baylibre.com>
Cc:     dri-devel <dri-devel@lists.freedesktop.org>,
        Mark Rutland <mark.rutland@arm.com>,
        devicetree@vger.kernel.org,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        Maxime Ripard <maxime.ripard@bootlin.com>,
        linux-sunxi <linux-sunxi@googlegroups.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        David Airlie <airlied@linux.ie>, Chen-Yu Tsai <wens@csie.org>,
        Icenowy Zheng <icenowy@aosc.io>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Mon, Dec 3, 2018 at 6:25 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Am Dienstag, 27. November 2018, 08:42:49 CET schrieb Icenowy Zheng:
> > Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the
> > Midgard GPU product line.
> >
> > Add binding for the H6 Mali Midgard GPU.
> >
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> >  .../devicetree/bindings/gpu/arm,mali-midgard.txt    | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
> > index 02f870cd60e6..c897dd7be48f 100644
> > --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
> > @@ -18,6 +18,7 @@ Required properties:
> >      + "amlogic,meson-gxm-mali"
> >      + "rockchip,rk3288-mali"
> >      + "rockchip,rk3399-mali"
> > +    + "allwinner,sun50i-h6-mali"
>
> I'd think you might want to keep an alphabetical sorting here, aka
> above amlogic, otherwise the list will probably become hard to read
> at some later point.
>
>
> >  - reg : Physical base address of the device and length of the register area.
> >
> > @@ -44,6 +45,18 @@ Optional properties:
> >    for details.
> >
> >
> > +Vendor-specific bindings
> > +------------------------
> > +
> > +The Mali GPU is integrated very differently from one SoC to
> > +another. In order to accomodate those differences, you have the option
> > +to specify one more vendor-specific compatible, among:
> > +
> > +  - allwinner,sun50i-h6-mali
> > +    Required properties:
> > +      * resets: phandle to the reset line for the GPU
>
> While this paragraph is similar to how it is done in Utgard, I'm
> wondering why we cannot just describe the "resets" as regular
> optional property above that.

Optional is fine, but I don't want to see every vendor doing their own
definition (there's a similar patch for meson[1]). Please first figure
out how many resets the IP block has. ARM should help as they were
eager for me to accept this binding in the first place. Then we can
see if vendors have extra resets.

Rob

[1] https://patchwork.ozlabs.org/patch/1010406/