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[209.132.180.67]) by mx.google.com with ESMTP id i12si13564028pgq.466.2018.12.12.00.49.44; Wed, 12 Dec 2018 00:50:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbeLLIsu (ORCPT + 99 others); Wed, 12 Dec 2018 03:48:50 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57052 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726519AbeLLIst (ORCPT ); Wed, 12 Dec 2018 03:48:49 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id wBC8kD7l031600; Wed, 12 Dec 2018 09:48:29 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2p85qk5pt1-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 12 Dec 2018 09:48:29 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 49C9731; Wed, 12 Dec 2018 08:48:28 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2501C275D; Wed, 12 Dec 2018 08:48:28 +0000 (GMT) Received: from localhost (10.75.127.51) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 12 Dec 2018 09:48:27 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , Subject: [PATCH v2 1/3] dt-bindings: stm32: syscon: add clock support Date: Wed, 12 Dec 2018 09:48:13 +0100 Message-ID: <1544604495-4082-2-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1544604495-4082-1-git-send-email-fabrice.gasnier@st.com> References: <1544604495-4082-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-12-12_02:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 system configuration controller registers needs to be clocked. Document clock support on stm32-syscon. Signed-off-by: Fabrice Gasnier --- Changes in v2: - move clocks to specific bindings using syscon as per Rob's comment --- Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt index 99980ae..c92d411 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt +++ b/Documentation/devicetree/bindings/arm/stm32/stm32-syscon.txt @@ -5,10 +5,12 @@ Properties: - " st,stm32mp157-syscfg " - for stm32mp157 based SoCs, second value must be always "syscon". - reg : offset and length of the register set. + - clocks: phandle to the syscfg clock Example: syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; }; -- 1.9.1