Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp1610002imu; Wed, 12 Dec 2018 00:50:34 -0800 (PST) X-Google-Smtp-Source: AFSGD/V4xt9HUjKysuORAwUmJRG78mLDC6AtqqNTo2KdrI7DeKWT96ua/98HCe1ZbKTf+IgZp8as X-Received: by 2002:a62:cf02:: with SMTP id b2mr20190933pfg.183.1544604634068; Wed, 12 Dec 2018 00:50:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544604634; cv=none; d=google.com; s=arc-20160816; b=a6GyyA+Mt6q/dp37q2Y3hBs5g3oIEcmoORlTdSizC2/M/m+/MonfE1/MOnIYAobO5x ZF2B+NCB7j3buSJkxx1lVuPTW4+rmEeN/Qv9LEIthIdYj8LyB2n/8K7AiZxQ9+sgeI+H aBchhIa6hCfHHE9pmDpYeYA5P+hZllB7DtCKH0pe4P78lR1CAhwoWnfsl7K4/glq/oTs mjPUaEP0jHMHtqs+CRMJ6ctdrJyVVPQwy7mMsNRrCmc4ka+xU6aOyG23A0w3W8Cjyzcp rvrzS3Q2/Dp0Npg7uiEbEn9QnIR6md0NZMLESPsW585qWeui41gTK2RjPzAJOEEOUh+D n6Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=TF9Rls4BwefNh/zH36iPeSZ12hqQpNBsAE7SF1IYbow=; b=kr7eeWAvL6HpGJ7BokbDDa6DwT9V8CqhAYFOURTmK81Exu2GRDSXUj09I4xzMfMqrK HXjdi8LkUAlWdJc84RdLoKTy+h13qzaF4COo2IiM0pi+l7HOLu7FuVJ4lUBDtcAco1xy RQ8dyNWi6VILhEDTDP/vrj0r0b/Sp+O3RnCcpysxAxehKqBxJxyTUluVTnOiaaP6b5Yy yY3d5+53xgBW+JsxwMGd6/zRMe7JuSSIxONgUfxeTVD3B0ifFYakNLF1l818TM9NoXSs dLsFt5fkDLdegyhn5QV9k8rrEKrRwmrKuzey6Zn0rl8boZQjj8Usii35lHfmkcM4MTFE 6tYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 144si14545676pga.322.2018.12.12.00.49.56; Wed, 12 Dec 2018 00:50:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726794AbeLLIs7 (ORCPT + 99 others); Wed, 12 Dec 2018 03:48:59 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:11792 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726242AbeLLIsu (ORCPT ); Wed, 12 Dec 2018 03:48:50 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id wBC8jdo1000815; Wed, 12 Dec 2018 09:48:28 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2p84a3dc6t-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 12 Dec 2018 09:48:28 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7452938; Wed, 12 Dec 2018 08:48:27 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3D3E52761; Wed, 12 Dec 2018 08:48:27 +0000 (GMT) Received: from localhost (10.75.127.50) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 12 Dec 2018 09:48:26 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , Subject: [PATCH v2 0/3] mfd: syscon: Add optional clock support needed on stm32 Date: Wed, 12 Dec 2018 09:48:12 +0100 Message-ID: <1544604495-4082-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-12-12_02:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 syscfg registers are accessed using syscon. It needs syscfg clock to be enabled while accessing registers. This adds support for optional clock on syscon, and the relevant clock in stm32mp157 device tree. Changes in v2: - move clocks to specific bindings using syscon as per Rob's comment Fabrice Gasnier (3): dt-bindings: stm32: syscon: add clock support mfd: syscon: Add optional clock support ARM: dts: stm32: Add clock on stm32mp157c syscfg .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 2 ++ arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/mfd/syscon.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) -- 1.9.1