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[209.132.180.67]) by mx.google.com with ESMTP id e9si14517864plt.330.2018.12.12.02.12.51; Wed, 12 Dec 2018 02:13:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="uJT/Txo+"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727016AbeLLKLn (ORCPT + 99 others); Wed, 12 Dec 2018 05:11:43 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33606 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726727AbeLLKLm (ORCPT ); Wed, 12 Dec 2018 05:11:42 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBCABFJI024456; Wed, 12 Dec 2018 04:11:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1544609475; bh=iH0Lp4gBXB8vYc73hbi/YH5blhG9/eJTX5Ek/7SSJqg=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=uJT/Txo+UgIp/VWrtOZd7AjsxqtqvYeWPYhRkPCwuJvDSI6aNvDXUuhi6tQfu7Bum mpQq6cHgI4Jr4a/7u1dj0Rh9VCBe/OVFaT28OVyHtRTF0JXvntox2drzTFqB7qnSR5 uNsk7wJ+ppp3JtuD4bZ+Hud+0TFRN5KodqbW2hzg= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBCABF8j103535 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Dec 2018 04:11:15 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 12 Dec 2018 04:11:15 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 12 Dec 2018 04:11:15 -0600 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBCABBs2026575; Wed, 12 Dec 2018 04:11:12 -0600 Subject: Re: [PATCH] ARM: dts: omap5: Add l4 interconnect hierarchy and ti-sysc data To: Tony Lindgren , CC: Dave Gerlach , Faiz Abbas , Greg Kroah-Hartman , Keerthy , Nishanth Menon , Suman Anna , Tero Kristo , , , References: <20181115224546.61475-1-tony@atomide.com> From: Peter Ujfalusi Message-ID: <9b7e07ae-66f9-cedf-937d-b1c5c510e018@ti.com> Date: Wed, 12 Dec 2018 12:12:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.3 MIME-Version: 1.0 In-Reply-To: <20181115224546.61475-1-tony@atomide.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tony, On 16/11/2018 0.45, Tony Lindgren wrote: > Similar to commit 8f42cb7f64c7 ("ARM: dts: omap4: Add l4 interconnect > hierarchy and ti-sysc data"), let's add proper interconnect hierarchy > for l4 interconnect instances with the related ti-sysc interconnect > module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt. > > Using ti-sysc driver binding allows us to start dropping legacy platform > data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of > ti-sysc dts data. > > This data is generated based on platform data from a booted system > and the interconnect acces protection registers for ranges. To avoid > regressions, we initially validate the device tree provided data > against the existing platform data on boot. Reverting this patch in linux-next-20181210 will make the ethernet working again. bootlog w/ revert: https://pastebin.com/dpRk1xWv bootlog w/o revert: https://pastebin.com/PWrBttxd > > Cc: devicetree@vger.kernel.org > Signed-off-by: Tony Lindgren > --- > arch/arm/boot/dts/omap5-l4.dtsi | 2462 +++++++++++++++++++++++++++++++ > arch/arm/boot/dts/omap5.dtsi | 688 +-------- > 2 files changed, 2468 insertions(+), 682 deletions(-) > create mode 100644 arch/arm/boot/dts/omap5-l4.dtsi > > diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi > new file mode 100644 > --- /dev/null > +++ b/arch/arm/boot/dts/omap5-l4.dtsi > @@ -0,0 +1,2462 @@ > +&l4_cfg { /* 0x4a000000 */ > + compatible = "ti,omap5-l4-cfg", "simple-bus"; > + reg = <0x4a000000 0x800>, > + <0x4a000800 0x800>, > + <0x4a001000 0x1000>; > + reg-names = "ap", "la", "ia0"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ > + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ > + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ > + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ > + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ > + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ > + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ > + > + segment@0 { /* 0x4a000000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ > + <0x00001000 0x00001000 0x001000>, /* ap 1 */ > + <0x00000800 0x00000800 0x000800>, /* ap 2 */ > + <0x00002000 0x00002000 0x001000>, /* ap 3 */ > + <0x00003000 0x00003000 0x001000>, /* ap 4 */ > + <0x00004000 0x00004000 0x001000>, /* ap 5 */ > + <0x00005000 0x00005000 0x001000>, /* ap 6 */ > + <0x00056000 0x00056000 0x001000>, /* ap 7 */ > + <0x00057000 0x00057000 0x001000>, /* ap 8 */ > + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ > + <0x00058000 0x00058000 0x001000>, /* ap 10 */ > + <0x00062000 0x00062000 0x001000>, /* ap 11 */ > + <0x00063000 0x00063000 0x001000>, /* ap 12 */ > + <0x00008000 0x00008000 0x002000>, /* ap 21 */ > + <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ > + <0x00066000 0x00066000 0x001000>, /* ap 23 */ > + <0x00067000 0x00067000 0x001000>, /* ap 24 */ > + <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ > + <0x00060000 0x00060000 0x001000>, /* ap 70 */ > + <0x00064000 0x00064000 0x001000>, /* ap 71 */ > + <0x00065000 0x00065000 0x001000>, /* ap 72 */ > + <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ > + <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ > + <0x00070000 0x00070000 0x004000>, /* ap 79 */ > + <0x00074000 0x00074000 0x001000>, /* ap 80 */ > + <0x00075000 0x00075000 0x001000>, /* ap 81 */ > + <0x00076000 0x00076000 0x001000>, /* ap 82 */ > + <0x00020000 0x00020000 0x020000>, /* ap 109 */ > + <0x00040000 0x00040000 0x001000>, /* ap 110 */ > + <0x00059000 0x00059000 0x001000>; /* ap 111 */ > + > + target-module@2000 { /* 0x4a002000, ap 3 44.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0x2000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x2000 0x1000>; > + > + scm_core: scm@0 { > + compatible = "ti,omap5-scm-core", "simple-bus"; > + reg = <0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x800>; > + > + scm_conf: scm_conf@0 { > + compatible = "syscon"; > + reg = <0x0 0x800>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + }; > + > + scm_padconf_core: scm@800 { > + compatible = "ti,omap5-scm-padconf-core", > + "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x800 0x800>; > + > + omap5_pmx_core: pinmux@40 { > + compatible = "ti,omap5-padconf", > + "pinctrl-single"; > + reg = <0x40 0x01b6>; > + #address-cells = <1>; > + #size-cells = <0>; > + #pinctrl-cells = <1>; > + #interrupt-cells = <1>; > + interrupt-controller; > + pinctrl-single,register-width = <16>; > + pinctrl-single,function-mask = <0x7fff>; > + }; > + > + omap5_padconf_global: omap5_padconf_global@5a0 { > + compatible = "syscon", > + "simple-bus"; > + reg = <0x5a0 0xec>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x5a0 0xec>; > + > + pbias_regulator: pbias_regulator@60 { > + compatible = "ti,pbias-omap5", "ti,pbias-omap"; > + reg = <0x60 0x4>; > + syscon = <&omap5_padconf_global>; > + pbias_mmc_reg: pbias_mmc_omap5 { > + regulator-name = "pbias_mmc_omap5"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + }; > + }; > + }; > + }; > + }; > + > + target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0x4000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x4000 0x1000>; > + > + cm_core_aon: cm_core_aon@0 { > + compatible = "ti,omap5-cm-core-aon", > + "simple-bus"; > + reg = <0x0 0x2000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x1000>; > + > + cm_core_aon_clocks: clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cm_core_aon_clockdomains: clockdomains { > + }; > + }; > + }; > + > + target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0x8000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x8000 0x2000>; > + > + cm_core: cm_core@0 { > + compatible = "ti,omap5-cm-core", "simple-bus"; > + reg = <0x0 0x2000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x2000>; > + > + cm_core_clocks: clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cm_core_clockdomains: clockdomains { > + }; > + }; > + }; > + > + target-module@20000 { /* 0x4a020000, ap 109 08.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "usb_otg_ss"; > + reg = <0x20000 0x4>, > + <0x20010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = ; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x20000 0x20000>; > + > + usb3: omap_dwc3@0 { > + compatible = "ti,dwc3"; > + reg = <0x0 0x10000>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <1>; > + utmi-mode = <2>; > + ranges = <0 0 0x20000>; > + dwc3: dwc3@4a030000 { > + compatible = "snps,dwc3"; > + reg = <0x10000 0x10000>; > + interrupts = , > + , > + ; > + interrupt-names = "peripheral", > + "host", > + "otg"; > + phys = <&usb2_phy>, <&usb3_phy>; > + phy-names = "usb2-phy", "usb3-phy"; > + dr_mode = "peripheral"; > + }; > + }; > + }; > + > + target-module@56000 { /* 0x4a056000, ap 7 02.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "dma_system"; > + reg = <0x56000 0x4>, > + <0x5602c 0x4>, > + <0x56028 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_EMUFREE | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-midle = , > + , > + ; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ > + clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x56000 0x1000>; > + > + sdma: dma-controller@0 { > + compatible = "ti,omap4430-sdma"; > + reg = <0x0 0x1000>; > + interrupts = , > + , > + , > + ; > + #dma-cells = <1>; > + dma-channels = <32>; > + dma-requests = <127>; > + }; > + }; > + > + target-module@58000 { /* 0x4a058000, ap 10 06.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00058000 0x00001000>, > + <0x00001000 0x00059000 0x00001000>, > + <0x00002000 0x0005a000 0x00001000>, > + <0x00003000 0x0005b000 0x00001000>; > + }; > + > + target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x5e000 0x2000>; > + }; > + > + target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "usb_tll_hs"; > + reg = <0x62000 0x4>, > + <0x62010 0x4>, > + <0x62014 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x62000 0x1000>; > + > + usbhstll: usbhstll@0 { > + compatible = "ti,usbhs-tll"; > + reg = <0x0 0x1000>; > + interrupts = ; > + }; > + }; > + > + target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "usb_host_hs"; > + reg = <0x64000 0x4>, > + <0x64010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = ; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x64000 0x1000>; > + > + usbhshost: usbhshost@0 { > + compatible = "ti,usbhs-host"; > + reg = <0x0 0x800>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x1000>; > + clocks = <&l3init_60m_fclk>, > + <&xclk60mhsp1_ck>, > + <&xclk60mhsp2_ck>; > + clock-names = "refclk_60m_int", > + "refclk_60m_ext_p1", > + "refclk_60m_ext_p2"; > + > + usbhsohci: ohci@4a064800 { > + compatible = "ti,ohci-omap3"; > + reg = <0x800 0x400>; > + interrupts = ; > + remote-wakeup-connected; > + }; > + > + usbhsehci: ehci@4a064c00 { > + compatible = "ti,ehci-omap"; > + reg = <0xc00 0x400>; > + interrupts = ; > + }; > + }; > + }; > + > + target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "mmu_dsp"; > + reg = <0x66000 0x4>, > + <0x66010 0x4>, > + <0x66014 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ > + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x66000 0x1000>; > + > + /* mmu_dsp cannot be moved before reset driver */ > + status = "disabled"; > + }; > + > + target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x70000 0x4000>; > + }; > + > + target-module@75000 { /* 0x4a075000, ap 81 32.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x75000 0x1000>; > + }; > + }; > + > + segment@80000 { /* 0x4a080000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ > + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ > + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ > + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ > + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ > + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ > + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ > + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ > + <0x00074000 0x000f4000 0x001000>, /* ap 25 */ > + <0x00075000 0x000f5000 0x001000>, /* ap 26 */ > + <0x00076000 0x000f6000 0x001000>, /* ap 27 */ > + <0x00077000 0x000f7000 0x001000>, /* ap 28 */ > + <0x00036000 0x000b6000 0x001000>, /* ap 65 */ > + <0x00037000 0x000b7000 0x001000>, /* ap 66 */ > + <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ > + <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ > + <0x00000000 0x00080000 0x004000>, /* ap 83 */ > + <0x00004000 0x00084000 0x001000>, /* ap 84 */ > + <0x00005000 0x00085000 0x001000>, /* ap 85 */ > + <0x00006000 0x00086000 0x001000>, /* ap 86 */ > + <0x00007000 0x00087000 0x001000>, /* ap 87 */ > + <0x00008000 0x00088000 0x001000>, /* ap 88 */ > + <0x00010000 0x00090000 0x004000>, /* ap 89 */ > + <0x00014000 0x00094000 0x001000>, /* ap 90 */ > + <0x00015000 0x00095000 0x001000>, /* ap 91 */ > + <0x00016000 0x00096000 0x001000>, /* ap 92 */ > + <0x00017000 0x00097000 0x001000>, /* ap 93 */ > + <0x00018000 0x00098000 0x001000>, /* ap 94 */ > + <0x00020000 0x000a0000 0x004000>, /* ap 95 */ > + <0x00024000 0x000a4000 0x001000>, /* ap 96 */ > + <0x00025000 0x000a5000 0x001000>, /* ap 97 */ > + <0x00026000 0x000a6000 0x001000>, /* ap 98 */ > + <0x00027000 0x000a7000 0x001000>, /* ap 99 */ > + <0x00028000 0x000a8000 0x001000>; /* ap 100 */ > + > + target-module@0 { /* 0x4a080000, ap 83 28.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "ocp2scp1"; > + reg = <0x0 0x4>, > + <0x10 0x4>, > + <0x14 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00000000 0x00004000>, > + <0x00004000 0x00004000 0x00001000>, > + <0x00005000 0x00005000 0x00001000>, > + <0x00006000 0x00006000 0x00001000>, > + <0x00007000 0x00007000 0x00001000>; > + > + ocp2scp@0 { > + compatible = "ti,omap-ocp2scp"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0 0x20>; > + }; > + > + usb2_phy: usb2phy@4000 { > + compatible = "ti,omap-usb2"; > + reg = <0x4000 0x7c>; > + syscon-phy-power = <&scm_conf 0x300>; > + clocks = <&usb_phy_cm_clk32k>, > + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; > + clock-names = "wkupclk", "refclk"; > + #phy-cells = <0>; > + }; > + > + usb3_phy: usb3phy@4400 { > + compatible = "ti,omap-usb3"; > + reg = <0x4400 0x80>, > + <0x4800 0x64>, > + <0x4c00 0x40>; > + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > + syscon-phy-power = <&scm_conf 0x370>; > + clocks = <&usb_phy_cm_clk32k>, > + <&sys_clkin>, > + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; > + clock-names = "wkupclk", > + "sysclk", > + "refclk"; > + #phy-cells = <0>; > + }; > + }; > + > + target-module@10000 { /* 0x4a090000, ap 89 36.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "ocp2scp3"; > + reg = <0x10000 0x4>, > + <0x10010 0x4>, > + <0x10014 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00010000 0x00004000>, > + <0x00004000 0x00014000 0x00001000>, > + <0x00005000 0x00015000 0x00001000>, > + <0x00006000 0x00016000 0x00001000>, > + <0x00007000 0x00017000 0x00001000>; > + > + ocp2scp@0 { > + compatible = "ti,omap-ocp2scp"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x0 0x20>; > + ranges = <0 0 0x4000>; > + sata_phy: phy@4a096000 { > + compatible = "ti,phy-pipe3-sata"; > + reg = <0x6000 0x80>, /* phy_rx */ > + <0x4A096400 0x64>, /* phy_tx */ > + <0x4A096800 0x40>; /* pll_ctrl */ > + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > + syscon-phy-power = <&scm_conf 0x374>; > + clocks = <&sys_clkin>, > + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; > + clock-names = "sysclk", "refclk"; > + #phy-cells = <0>; > + }; > + }; > + }; > + > + target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00020000 0x00004000>, > + <0x00004000 0x00024000 0x00001000>, > + <0x00005000 0x00025000 0x00001000>, > + <0x00006000 0x00026000 0x00001000>, > + <0x00007000 0x00027000 0x00001000>; > + }; > + > + target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x36000 0x1000>; > + }; > + > + target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x4d000 0x1000>; > + }; > + > + target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x59000 0x1000>; > + }; > + > + target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x5b000 0x1000>; > + }; > + > + target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x5d000 0x1000>; > + }; > + > + target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x60000 0x1000>; > + }; > + > + target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mailbox"; > + reg = <0x74000 0x4>, > + <0x74010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = ; > + ti,sysc-sidle = , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ > + clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x74000 0x1000>; > + > + mailbox: mailbox@0 { > + compatible = "ti,omap4-mailbox"; > + reg = <0x0 0x200>; > + interrupts = ; > + #mbox-cells = <1>; > + ti,mbox-num-users = <3>; > + ti,mbox-num-fifos = <8>; > + mbox_ipu: mbox_ipu { > + ti,mbox-tx = <0 0 0>; > + ti,mbox-rx = <1 0 0>; > + }; > + mbox_dsp: mbox_dsp { > + ti,mbox-tx = <3 0 0>; > + ti,mbox-rx = <2 0 0>; > + }; > + }; > + }; > + > + target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "spinlock"; > + reg = <0x76000 0x4>, > + <0x76010 0x4>, > + <0x76014 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ > + clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x76000 0x1000>; > + > + hwspinlock: spinlock@0 { > + compatible = "ti,omap4-hwspinlock"; > + reg = <0x0 0x1000>; > + #hwlock-cells = <1>; > + }; > + }; > + }; > + > + segment@100000 { /* 0x4a100000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ > + <0x00003000 0x00103000 0x001000>, /* ap 60 */ > + <0x00008000 0x00108000 0x001000>, /* ap 61 */ > + <0x00009000 0x00109000 0x001000>, /* ap 62 */ > + <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ > + <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ > + <0x00040000 0x00140000 0x010000>, /* ap 101 */ > + <0x00050000 0x00150000 0x001000>; /* ap 102 */ > + > + target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x2000 0x1000>; > + }; > + > + target-module@8000 { /* 0x4a108000, ap 61 26.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x8000 0x1000>; > + }; > + > + target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xa000 0x1000>; > + }; > + > + target-module@40000 { /* 0x4a140000, ap 101 16.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x40000 0x10000>; > + }; > + }; > + > + segment@180000 { /* 0x4a180000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > + segment@200000 { /* 0x4a200000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ > + <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ > + <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ > + <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ > + <0x00006000 0x00206000 0x001000>, /* ap 33 */ > + <0x00007000 0x00207000 0x001000>, /* ap 34 */ > + <0x00004000 0x00204000 0x001000>, /* ap 35 */ > + <0x00005000 0x00205000 0x001000>, /* ap 36 */ > + <0x00012000 0x00212000 0x001000>, /* ap 37 */ > + <0x00013000 0x00213000 0x001000>, /* ap 38 */ > + <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ > + <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ > + <0x00010000 0x00210000 0x001000>, /* ap 41 */ > + <0x00011000 0x00211000 0x001000>, /* ap 42 */ > + <0x00016000 0x00216000 0x001000>, /* ap 43 */ > + <0x00017000 0x00217000 0x001000>, /* ap 44 */ > + <0x00014000 0x00214000 0x001000>, /* ap 45 */ > + <0x00015000 0x00215000 0x001000>, /* ap 46 */ > + <0x00018000 0x00218000 0x001000>, /* ap 47 */ > + <0x00019000 0x00219000 0x001000>, /* ap 48 */ > + <0x00020000 0x00220000 0x001000>, /* ap 49 */ > + <0x00021000 0x00221000 0x001000>, /* ap 50 */ > + <0x00026000 0x00226000 0x001000>, /* ap 51 */ > + <0x00027000 0x00227000 0x001000>, /* ap 52 */ > + <0x00028000 0x00228000 0x001000>, /* ap 53 */ > + <0x00029000 0x00229000 0x001000>, /* ap 54 */ > + <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ > + <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ > + <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ > + <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ > + <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ > + <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ > + <0x00024000 0x00224000 0x001000>, /* ap 75 */ > + <0x00025000 0x00225000 0x001000>, /* ap 76 */ > + <0x00002000 0x00202000 0x001000>, /* ap 103 */ > + <0x00003000 0x00203000 0x001000>, /* ap 104 */ > + <0x00008000 0x00208000 0x001000>, /* ap 105 */ > + <0x00009000 0x00209000 0x001000>, /* ap 106 */ > + <0x00022000 0x00222000 0x001000>, /* ap 107 */ > + <0x00023000 0x00223000 0x001000>; /* ap 108 */ > + > + target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x2000 0x1000>; > + }; > + > + target-module@4000 { /* 0x4a204000, ap 35 46.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x4000 0x1000>; > + }; > + > + target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x6000 0x1000>; > + }; > + > + target-module@8000 { /* 0x4a208000, ap 105 34.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x8000 0x1000>; > + }; > + > + target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xa000 0x1000>; > + }; > + > + target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xc000 0x1000>; > + }; > + > + target-module@10000 { /* 0x4a210000, ap 41 56.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x10000 0x1000>; > + }; > + > + target-module@12000 { /* 0x4a212000, ap 37 52.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x12000 0x1000>; > + }; > + > + target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x14000 0x1000>; > + }; > + > + target-module@16000 { /* 0x4a216000, ap 43 42.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x16000 0x1000>; > + }; > + > + target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x18000 0x1000>; > + }; > + > + target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x1a000 0x1000>; > + }; > + > + target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x1c000 0x1000>; > + }; > + > + target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x1e000 0x1000>; > + }; > + > + target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x20000 0x1000>; > + }; > + > + target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x22000 0x1000>; > + }; > + > + target-module@24000 { /* 0x4a224000, ap 75 48.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x24000 0x1000>; > + }; > + > + target-module@26000 { /* 0x4a226000, ap 51 24.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x26000 0x1000>; > + }; > + > + target-module@28000 { /* 0x4a228000, ap 53 38.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x28000 0x1000>; > + }; > + > + target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x2a000 0x1000>; > + }; > + }; > + > + segment@280000 { /* 0x4a280000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > + segment@300000 { /* 0x4a300000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > +&l4_per { /* 0x48000000 */ > + compatible = "ti,omap5-l4-per", "simple-bus"; > + reg = <0x48000000 0x800>, > + <0x48000800 0x800>, > + <0x48001000 0x400>, > + <0x48001400 0x400>, > + <0x48001800 0x400>, > + <0x48001c00 0x400>; > + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ > + <0x00200000 0x48200000 0x200000>; /* segment 1 */ > + > + segment@0 { /* 0x48000000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ > + <0x00001000 0x00001000 0x000400>, /* ap 1 */ > + <0x00000800 0x00000800 0x000800>, /* ap 2 */ > + <0x00020000 0x00020000 0x001000>, /* ap 3 */ > + <0x00021000 0x00021000 0x001000>, /* ap 4 */ > + <0x00032000 0x00032000 0x001000>, /* ap 5 */ > + <0x00033000 0x00033000 0x001000>, /* ap 6 */ > + <0x00034000 0x00034000 0x001000>, /* ap 7 */ > + <0x00035000 0x00035000 0x001000>, /* ap 8 */ > + <0x00036000 0x00036000 0x001000>, /* ap 9 */ > + <0x00037000 0x00037000 0x001000>, /* ap 10 */ > + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ > + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ > + <0x00055000 0x00055000 0x001000>, /* ap 13 */ > + <0x00056000 0x00056000 0x001000>, /* ap 14 */ > + <0x00057000 0x00057000 0x001000>, /* ap 15 */ > + <0x00058000 0x00058000 0x001000>, /* ap 16 */ > + <0x00059000 0x00059000 0x001000>, /* ap 17 */ > + <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ > + <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ > + <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ > + <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ > + <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ > + <0x00060000 0x00060000 0x001000>, /* ap 23 */ > + <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ > + <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ > + <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ > + <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ > + <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ > + <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ > + <0x00070000 0x00070000 0x001000>, /* ap 30 */ > + <0x00071000 0x00071000 0x001000>, /* ap 31 */ > + <0x00072000 0x00072000 0x001000>, /* ap 32 */ > + <0x00073000 0x00073000 0x001000>, /* ap 33 */ > + <0x00061000 0x00061000 0x001000>, /* ap 34 */ > + <0x00053000 0x00053000 0x001000>, /* ap 35 */ > + <0x00054000 0x00054000 0x001000>, /* ap 36 */ > + <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ > + <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ > + <0x00078000 0x00078000 0x001000>, /* ap 39 */ > + <0x00079000 0x00079000 0x001000>, /* ap 40 */ > + <0x00086000 0x00086000 0x001000>, /* ap 41 */ > + <0x00087000 0x00087000 0x001000>, /* ap 42 */ > + <0x00088000 0x00088000 0x001000>, /* ap 43 */ > + <0x00089000 0x00089000 0x001000>, /* ap 44 */ > + <0x00051000 0x00051000 0x001000>, /* ap 45 */ > + <0x00052000 0x00052000 0x001000>, /* ap 46 */ > + <0x00098000 0x00098000 0x001000>, /* ap 47 */ > + <0x00099000 0x00099000 0x001000>, /* ap 48 */ > + <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ > + <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ > + <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ > + <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ > + <0x00068000 0x00068000 0x001000>, /* ap 53 */ > + <0x00069000 0x00069000 0x001000>, /* ap 54 */ > + <0x00090000 0x00090000 0x002000>, /* ap 55 */ > + <0x00092000 0x00092000 0x001000>, /* ap 56 */ > + <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ > + <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ > + <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ > + <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ > + <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ > + <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ > + <0x00066000 0x00066000 0x001000>, /* ap 63 */ > + <0x00067000 0x00067000 0x001000>, /* ap 64 */ > + <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ > + <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ > + <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ > + <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ > + <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ > + <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ > + <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ > + <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ > + <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ > + <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ > + <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ > + <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ > + <0x00001400 0x00001400 0x000400>, /* ap 77 */ > + <0x00001800 0x00001800 0x000400>, /* ap 78 */ > + <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ > + <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ > + <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ > + <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ > + <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ > + <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ > + > + target-module@20000 { /* 0x48020000, ap 3 04.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart3"; > + reg = <0x20050 0x4>, > + <0x20054 0x4>, > + <0x20058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + ti,no-reset-on-init; > + ti,no-idle-on-init; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x20000 0x1000>; > + > + uart3: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@32000 { /* 0x48032000, ap 5 3e.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer2"; > + reg = <0x32000 0x4>, > + <0x32010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x32000 0x1000>; > + > + timer2: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + }; > + }; > + > + target-module@34000 { /* 0x48034000, ap 7 46.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer3"; > + reg = <0x34000 0x4>, > + <0x34010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x34000 0x1000>; > + > + timer3: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + }; > + }; > + > + target-module@36000 { /* 0x48036000, ap 9 4e.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer4"; > + reg = <0x36000 0x4>, > + <0x36010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x36000 0x1000>; > + > + timer4: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + }; > + }; > + > + target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer9"; > + reg = <0x3e000 0x4>, > + <0x3e010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x3e000 0x1000>; > + > + timer9: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + ti,timer-pwm; > + }; > + }; > + > + target-module@51000 { /* 0x48051000, ap 45 2e.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio7"; > + reg = <0x51000 0x4>, > + <0x51010 0x4>, > + <0x51114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x51000 0x1000>; > + > + gpio7: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@53000 { /* 0x48053000, ap 35 36.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio8"; > + reg = <0x53000 0x4>, > + <0x53010 0x4>, > + <0x53114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x53000 0x1000>; > + > + gpio8: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@55000 { /* 0x48055000, ap 13 0e.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio2"; > + reg = <0x55000 0x4>, > + <0x55010 0x4>, > + <0x55114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x55000 0x1000>; > + > + gpio2: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@57000 { /* 0x48057000, ap 15 06.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio3"; > + reg = <0x57000 0x4>, > + <0x57010 0x4>, > + <0x57114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x57000 0x1000>; > + > + gpio3: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@59000 { /* 0x48059000, ap 17 16.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio4"; > + reg = <0x59000 0x4>, > + <0x59010 0x4>, > + <0x59114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x59000 0x1000>; > + > + gpio4: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio5"; > + reg = <0x5b000 0x4>, > + <0x5b010 0x4>, > + <0x5b114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x5b000 0x1000>; > + > + gpio5: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio6"; > + reg = <0x5d000 0x4>, > + <0x5d010 0x4>, > + <0x5d114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, > + <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x5d000 0x1000>; > + > + gpio6: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@60000 { /* 0x48060000, ap 23 24.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "i2c3"; > + reg = <0x60000 0x8>, > + <0x60010 0x8>, > + <0x60090 0x8>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x60000 0x1000>; > + > + i2c3: i2c@0 { > + compatible = "ti,omap4-i2c"; > + reg = <0x0 0x100>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + target-module@66000 { /* 0x48066000, ap 63 4c.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart5"; > + reg = <0x66050 0x4>, > + <0x66054 0x4>, > + <0x66058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x66000 0x1000>; > + > + uart5: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@68000 { /* 0x48068000, ap 53 54.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart6"; > + reg = <0x68050 0x4>, > + <0x68054 0x4>, > + <0x68058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x68000 0x1000>; > + > + uart6: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart1"; > + reg = <0x6a050 0x4>, > + <0x6a054 0x4>, > + <0x6a058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x6a000 0x1000>; > + > + uart1: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart2"; > + reg = <0x6c050 0x4>, > + <0x6c054 0x4>, > + <0x6c058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x6c000 0x1000>; > + > + uart2: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "uart4"; > + reg = <0x6e050 0x4>, > + <0x6e054 0x4>, > + <0x6e058 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x6e000 0x1000>; > + > + uart4: serial@0 { > + compatible = "ti,omap4-uart"; > + reg = <0x0 0x100>; > + interrupts = ; > + clock-frequency = <48000000>; > + }; > + }; > + > + target-module@70000 { /* 0x48070000, ap 30 14.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "i2c1"; > + reg = <0x70000 0x8>, > + <0x70010 0x8>, > + <0x70090 0x8>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x70000 0x1000>; > + > + i2c1: i2c@0 { > + compatible = "ti,omap4-i2c"; > + reg = <0x0 0x100>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + target-module@72000 { /* 0x48072000, ap 32 1c.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "i2c2"; > + reg = <0x72000 0x8>, > + <0x72010 0x8>, > + <0x72090 0x8>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x72000 0x1000>; > + > + i2c2: i2c@0 { > + compatible = "ti,omap4-i2c"; > + reg = <0x0 0x100>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + target-module@78000 { /* 0x48078000, ap 39 12.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x78000 0x1000>; > + }; > + > + target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "i2c4"; > + reg = <0x7a000 0x8>, > + <0x7a010 0x8>, > + <0x7a090 0x8>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x7a000 0x1000>; > + > + i2c4: i2c@0 { > + compatible = "ti,omap4-i2c"; > + reg = <0x0 0x100>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "i2c5"; > + reg = <0x7c000 0x8>, > + <0x7c010 0x8>, > + <0x7c090 0x8>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | > + SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x7c000 0x1000>; > + > + i2c5: i2c@0 { > + compatible = "ti,omap4-i2c"; > + reg = <0x0 0x100>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + target-module@86000 { /* 0x48086000, ap 41 5e.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer10"; > + reg = <0x86000 0x4>, > + <0x86010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x86000 0x1000>; > + > + timer10: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + ti,timer-pwm; > + }; > + }; > + > + target-module@88000 { /* 0x48088000, ap 43 66.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer11"; > + reg = <0x88000 0x4>, > + <0x88010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x88000 0x1000>; > + > + timer11: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + ti,timer-pwm; > + }; > + }; > + > + target-module@90000 { /* 0x48090000, ap 55 1a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x90000 0x2000>; > + }; > + > + target-module@98000 { /* 0x48098000, ap 47 08.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mcspi1"; > + reg = <0x98000 0x4>, > + <0x98010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x98000 0x1000>; > + > + mcspi1: spi@0 { > + compatible = "ti,omap4-mcspi"; > + reg = <0x0 0x200>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + ti,spi-num-cs = <4>; > + dmas = <&sdma 35>, > + <&sdma 36>, > + <&sdma 37>, > + <&sdma 38>, > + <&sdma 39>, > + <&sdma 40>, > + <&sdma 41>, > + <&sdma 42>; > + dma-names = "tx0", "rx0", "tx1", "rx1", > + "tx2", "rx2", "tx3", "rx3"; > + }; > + }; > + > + target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mcspi2"; > + reg = <0x9a000 0x4>, > + <0x9a010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x9a000 0x1000>; > + > + mcspi2: spi@0 { > + compatible = "ti,omap4-mcspi"; > + reg = <0x0 0x200>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + ti,spi-num-cs = <2>; > + dmas = <&sdma 43>, > + <&sdma 44>, > + <&sdma 45>, > + <&sdma 46>; > + dma-names = "tx0", "rx0", "tx1", "rx1"; > + }; > + }; > + > + target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mmc1"; > + reg = <0x9c000 0x4>, > + <0x9c010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x9c000 0x1000>; > + > + mmc1: mmc@0 { > + compatible = "ti,omap4-hsmmc"; > + reg = <0x0 0x400>; > + interrupts = ; > + ti,dual-volt; > + ti,needs-special-reset; > + dmas = <&sdma 61>, <&sdma 62>; > + dma-names = "tx", "rx"; > + pbias-supply = <&pbias_mmc_reg>; > + }; > + }; > + > + target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xa2000 0x1000>; > + }; > + > + target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x000a4000 0x00001000>, > + <0x00001000 0x000a5000 0x00001000>; > + }; > + > + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xa8000 0x4000>; > + }; > + > + target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mmc3"; > + reg = <0xad000 0x4>, > + <0xad010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xad000 0x1000>; > + > + mmc3: mmc@0 { > + compatible = "ti,omap4-hsmmc"; > + reg = <0x0 0x400>; > + interrupts = ; > + ti,needs-special-reset; > + dmas = <&sdma 77>, <&sdma 78>; > + dma-names = "tx", "rx"; > + }; > + }; > + > + target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xb2000 0x1000>; > + }; > + > + target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mmc2"; > + reg = <0xb4000 0x4>, > + <0xb4010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ > + clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xb4000 0x1000>; > + > + mmc2: mmc@0 { > + compatible = "ti,omap4-hsmmc"; > + reg = <0x0 0x400>; > + interrupts = ; > + ti,needs-special-reset; > + dmas = <&sdma 47>, <&sdma 48>; > + dma-names = "tx", "rx"; > + }; > + }; > + > + target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mcspi3"; > + reg = <0xb8000 0x4>, > + <0xb8010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xb8000 0x1000>; > + > + mcspi3: spi@0 { > + compatible = "ti,omap4-mcspi"; > + reg = <0x0 0x200>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + ti,spi-num-cs = <2>; > + dmas = <&sdma 15>, <&sdma 16>; > + dma-names = "tx0", "rx0"; > + }; > + }; > + > + target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mcspi4"; > + reg = <0xba000 0x4>, > + <0xba010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xba000 0x1000>; > + > + mcspi4: spi@0 { > + compatible = "ti,omap4-mcspi"; > + reg = <0x0 0x200>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + ti,spi-num-cs = <1>; > + dmas = <&sdma 70>, <&sdma 71>; > + dma-names = "tx0", "rx0"; > + }; > + }; > + > + target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mmc4"; > + reg = <0xd1000 0x4>, > + <0xd1010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xd1000 0x1000>; > + > + mmc4: mmc@0 { > + compatible = "ti,omap4-hsmmc"; > + reg = <0x0 0x400>; > + interrupts = ; > + ti,needs-special-reset; > + dmas = <&sdma 57>, <&sdma 58>; > + dma-names = "tx", "rx"; > + }; > + }; > + > + target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + ti,hwmods = "mmc5"; > + reg = <0xd5000 0x4>, > + <0xd5010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-midle = , > + , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ > + clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xd5000 0x1000>; > + > + mmc5: mmc@0 { > + compatible = "ti,omap4-hsmmc"; > + reg = <0x0 0x400>; > + interrupts = ; > + ti,needs-special-reset; > + dmas = <&sdma 59>, <&sdma 60>; > + dma-names = "tx", "rx"; > + }; > + }; > + }; > + > + segment@200000 { /* 0x48200000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > + > +&l4_wkup { /* 0x4ae00000 */ > + compatible = "ti,omap5-l4-wkup", "simple-bus"; > + reg = <0x4ae00000 0x800>, > + <0x4ae00800 0x800>, > + <0x4ae01000 0x1000>; > + reg-names = "ap", "la", "ia0"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ > + <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ > + <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ > + > + segment@0 { /* 0x4ae00000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ > + <0x00001000 0x00001000 0x001000>, /* ap 1 */ > + <0x00000800 0x00000800 0x000800>, /* ap 2 */ > + <0x00006000 0x00006000 0x002000>, /* ap 3 */ > + <0x00008000 0x00008000 0x001000>, /* ap 4 */ > + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ > + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ > + <0x00004000 0x00004000 0x001000>, /* ap 17 */ > + <0x00005000 0x00005000 0x001000>, /* ap 18 */ > + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ > + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ > + > + target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "counter_32k"; > + reg = <0x4000 0x4>, > + <0x4010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-sidle = , > + ; > + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ > + clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x4000 0x1000>; > + > + counter32k: counter@0 { > + compatible = "ti,omap-counter32k"; > + reg = <0x0 0x40>; > + }; > + }; > + > + target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0x6000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x6000 0x2000>; > + > + prm: prm@0 { > + compatible = "ti,omap5-prm", "simple-bus"; > + reg = <0x0 0x2000>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x2000>; > + > + prm_clocks: clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + prm_clockdomains: clockdomains { > + }; > + }; > + }; > + > + target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0xa000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xa000 0x1000>; > + > + scrm: scrm@0 { > + compatible = "ti,omap5-scrm"; > + reg = <0x0 0x1000>; > + > + scrm_clocks: clocks { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + scrm_clockdomains: clockdomains { > + }; > + }; > + }; > + > + target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ > + compatible = "ti,sysc-omap4", "ti,sysc"; > + reg = <0xc000 0x4>; > + reg-names = "rev"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xc000 0x1000>; > + > + omap5_pmx_wkup: pinmux@840 { > + compatible = "ti,omap5-padconf", > + "pinctrl-single"; > + reg = <0x840 0x003c>; > + #address-cells = <1>; > + #size-cells = <0>; > + #pinctrl-cells = <1>; > + #interrupt-cells = <1>; > + interrupt-controller; > + pinctrl-single,register-width = <16>; > + pinctrl-single,function-mask = <0x7fff>; > + }; > + > + omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { > + compatible = "ti,omap5-scm-wkup-pad-conf", > + "simple-bus"; > + reg = <0xda0 0x60>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x60>; > + > + scm_wkup_pad_conf: scm_conf@0 { > + compatible = "syscon", "simple-bus"; > + reg = <0x0 0x60>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x60>; > + > + scm_wkup_pad_conf_clocks: clocks@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > + }; > + > + segment@10000 { /* 0x4ae10000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ > + <0x00001000 0x00011000 0x001000>, /* ap 6 */ > + <0x00004000 0x00014000 0x001000>, /* ap 7 */ > + <0x00005000 0x00015000 0x001000>, /* ap 8 */ > + <0x00008000 0x00018000 0x001000>, /* ap 9 */ > + <0x00009000 0x00019000 0x001000>, /* ap 10 */ > + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ > + <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ > + > + target-module@0 { /* 0x4ae10000, ap 5 10.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "gpio1"; > + reg = <0x0 0x4>, > + <0x10 0x4>, > + <0x114 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ > + clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, > + <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; > + clock-names = "fck", "dbclk"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x1000>; > + > + gpio1: gpio@0 { > + compatible = "ti,omap4-gpio"; > + reg = <0x0 0x200>; > + interrupts = ; > + ti,gpio-always-on; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "wd_timer2"; > + reg = <0x4000 0x4>, > + <0x4010 0x4>, > + <0x4014 0x4>; > + reg-names = "rev", "sysc", "syss"; > + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | > + SYSC_OMAP2_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ > + clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x4000 0x1000>; > + > + wdt2: wdt@0 { > + compatible = "ti,omap5-wdt", "ti,omap3-wdt"; > + reg = <0x0 0x80>; > + interrupts = ; > + }; > + }; > + > + target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ > + compatible = "ti,sysc-omap4-timer", "ti,sysc"; > + ti,hwmods = "timer1"; > + reg = <0x8000 0x4>, > + <0x8010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | > + SYSC_OMAP4_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + , > + ; > + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ > + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x8000 0x1000>; > + > + timer1: timer@0 { > + compatible = "ti,omap5430-timer"; > + reg = <0x0 0x80>; > + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; > + clock-names = "fck"; > + interrupts = ; > + ti,timer-alwon; > + }; > + }; > + > + target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "kbd"; > + reg = <0xc000 0x4>, > + <0xc010 0x4>; > + reg-names = "rev", "sysc"; > + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | > + SYSC_OMAP2_SOFTRESET)>; > + ti,sysc-sidle = , > + , > + ; > + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ > + clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; > + clock-names = "fck"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xc000 0x1000>; > + > + keypad: keypad@0 { > + compatible = "ti,omap4-keypad"; > + reg = <0x0 0x400>; > + }; > + }; > + }; > + > + segment@20000 { /* 0x4ae20000 */ > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ > + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ > + <0x00000000 0x00020000 0x001000>, /* ap 21 */ > + <0x00001000 0x00021000 0x001000>, /* ap 22 */ > + <0x00002000 0x00022000 0x001000>, /* ap 23 */ > + <0x00003000 0x00023000 0x001000>, /* ap 24 */ > + <0x00007000 0x00027000 0x000400>, /* ap 25 */ > + <0x00008000 0x00028000 0x000800>, /* ap 26 */ > + <0x00009000 0x00029000 0x000100>, /* ap 27 */ > + <0x00008800 0x00028800 0x000200>, /* ap 28 */ > + <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ > + > + target-module@0 { /* 0x4ae20000, ap 21 04.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x1000>; > + }; > + > + target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x2000 0x1000>; > + }; > + > + target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ > + compatible = "ti,sysc"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00000000 0x00006000 0x00001000>, > + <0x00001000 0x00007000 0x00000400>, > + <0x00002000 0x00008000 0x00000800>, > + <0x00002800 0x00008800 0x00000200>, > + <0x00002a00 0x00008a00 0x00000100>, > + <0x00003000 0x00009000 0x00000100>; > + }; > + }; > +}; > + > diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi > --- a/arch/arm/boot/dts/omap5.dtsi > +++ b/arch/arm/boot/dts/omap5.dtsi > @@ -7,6 +7,7 @@ > * Based on "omap4.dtsi" > */ > > +#include > #include > #include > #include > @@ -151,178 +152,13 @@ > interrupts = , > ; > > - l4_cfg: l4@4a000000 { > - compatible = "ti,omap5-l4-cfg", "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x4a000000 0x22a000>; > - > - scm_core: scm@2000 { > - compatible = "ti,omap5-scm-core", "simple-bus"; > - reg = <0x2000 0x1000>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x2000 0x800>; > - > - scm_conf: scm_conf@0 { > - compatible = "syscon"; > - reg = <0x0 0x800>; > - #address-cells = <1>; > - #size-cells = <1>; > - }; > - }; > - > - scm_padconf_core: scm@2800 { > - compatible = "ti,omap5-scm-padconf-core", > - "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x2800 0x800>; > - > - omap5_pmx_core: pinmux@40 { > - compatible = "ti,omap5-padconf", > - "pinctrl-single"; > - reg = <0x40 0x01b6>; > - #address-cells = <1>; > - #size-cells = <0>; > - #pinctrl-cells = <1>; > - #interrupt-cells = <1>; > - interrupt-controller; > - pinctrl-single,register-width = <16>; > - pinctrl-single,function-mask = <0x7fff>; > - }; > - > - omap5_padconf_global: omap5_padconf_global@5a0 { > - compatible = "syscon", > - "simple-bus"; > - reg = <0x5a0 0xec>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x5a0 0xec>; > - > - pbias_regulator: pbias_regulator@60 { > - compatible = "ti,pbias-omap5", "ti,pbias-omap"; > - reg = <0x60 0x4>; > - syscon = <&omap5_padconf_global>; > - pbias_mmc_reg: pbias_mmc_omap5 { > - regulator-name = "pbias_mmc_omap5"; > - regulator-min-microvolt = <1800000>; > - regulator-max-microvolt = <3300000>; > - }; > - }; > - }; > - }; > - > - cm_core_aon: cm_core_aon@4000 { > - compatible = "ti,omap5-cm-core-aon", > - "simple-bus"; > - reg = <0x4000 0x2000>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x4000 0x2000>; > - > - cm_core_aon_clocks: clocks { > - #address-cells = <1>; > - #size-cells = <0>; > - }; > - > - cm_core_aon_clockdomains: clockdomains { > - }; > - }; > - > - cm_core: cm_core@8000 { > - compatible = "ti,omap5-cm-core", "simple-bus"; > - reg = <0x8000 0x3000>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x8000 0x3000>; > - > - cm_core_clocks: clocks { > - #address-cells = <1>; > - #size-cells = <0>; > - }; > - > - cm_core_clockdomains: clockdomains { > - }; > - }; > + l4_wkup: interconnect@4ae00000 { > }; > > - l4_wkup: l4@4ae00000 { > - compatible = "ti,omap5-l4-wkup", "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x4ae00000 0x2b000>; > - > - counter32k: counter@4000 { > - compatible = "ti,omap-counter32k"; > - reg = <0x4000 0x40>; > - ti,hwmods = "counter_32k"; > - }; > - > - prm: prm@6000 { > - compatible = "ti,omap5-prm", "simple-bus"; > - reg = <0x6000 0x3000>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x6000 0x3000>; > - > - prm_clocks: clocks { > - #address-cells = <1>; > - #size-cells = <0>; > - }; > - > - prm_clockdomains: clockdomains { > - }; > - }; > - > - scrm: scrm@a000 { > - compatible = "ti,omap5-scrm"; > - reg = <0xa000 0x2000>; > - > - scrm_clocks: clocks { > - #address-cells = <1>; > - #size-cells = <0>; > - }; > - > - scrm_clockdomains: clockdomains { > - }; > - }; > - > - omap5_pmx_wkup: pinmux@c840 { > - compatible = "ti,omap5-padconf", > - "pinctrl-single"; > - reg = <0xc840 0x003c>; > - #address-cells = <1>; > - #size-cells = <0>; > - #pinctrl-cells = <1>; > - #interrupt-cells = <1>; > - interrupt-controller; > - pinctrl-single,register-width = <16>; > - pinctrl-single,function-mask = <0x7fff>; > - }; > - > - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 { > - compatible = "ti,omap5-scm-wkup-pad-conf", > - "simple-bus"; > - reg = <0xcda0 0x60>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0xcda0 0x60>; > - > - scm_wkup_pad_conf: scm_conf@0 { > - compatible = "syscon", "simple-bus"; > - reg = <0x0 0x60>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x0 0x60>; > + l4_cfg: interconnect@4a000000 { > + }; > > - scm_wkup_pad_conf_clocks: clocks@0 { > - #address-cells = <1>; > - #size-cells = <0>; > - }; > - }; > - }; > + l4_per: interconnect@48000000 { > }; > > ocmcram: ocmcram@40300000 { > @@ -330,108 +166,6 @@ > reg = <0x40300000 0x20000>; /* 128k */ > }; > > - sdma: dma-controller@4a056000 { > - compatible = "ti,omap4430-sdma"; > - reg = <0x4a056000 0x1000>; > - interrupts = , > - , > - , > - ; > - #dma-cells = <1>; > - dma-channels = <32>; > - dma-requests = <127>; > - ti,hwmods = "dma_system"; > - }; > - > - gpio1: gpio@4ae10000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x4ae10000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio1"; > - ti,gpio-always-on; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio2: gpio@48055000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x48055000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio2"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio3: gpio@48057000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x48057000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio3"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio4: gpio@48059000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x48059000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio4"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio5: gpio@4805b000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x4805b000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio5"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio6: gpio@4805d000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x4805d000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio6"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio7: gpio@48051000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x48051000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio7"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > - gpio8: gpio@48053000 { > - compatible = "ti,omap4-gpio"; > - reg = <0x48053000 0x200>; > - interrupts = ; > - ti,hwmods = "gpio8"; > - gpio-controller; > - #gpio-cells = <2>; > - interrupt-controller; > - #interrupt-cells = <2>; > - }; > - > gpmc: gpmc@50000000 { > compatible = "ti,omap4430-gpmc"; > reg = <0x50000000 0x1000>; > @@ -451,217 +185,6 @@ > #gpio-cells = <2>; > }; > > - i2c1: i2c@48070000 { > - compatible = "ti,omap4-i2c"; > - reg = <0x48070000 0x100>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "i2c1"; > - }; > - > - i2c2: i2c@48072000 { > - compatible = "ti,omap4-i2c"; > - reg = <0x48072000 0x100>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "i2c2"; > - }; > - > - i2c3: i2c@48060000 { > - compatible = "ti,omap4-i2c"; > - reg = <0x48060000 0x100>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "i2c3"; > - }; > - > - i2c4: i2c@4807a000 { > - compatible = "ti,omap4-i2c"; > - reg = <0x4807a000 0x100>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "i2c4"; > - }; > - > - i2c5: i2c@4807c000 { > - compatible = "ti,omap4-i2c"; > - reg = <0x4807c000 0x100>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "i2c5"; > - }; > - > - hwspinlock: spinlock@4a0f6000 { > - compatible = "ti,omap4-hwspinlock"; > - reg = <0x4a0f6000 0x1000>; > - ti,hwmods = "spinlock"; > - #hwlock-cells = <1>; > - }; > - > - mcspi1: spi@48098000 { > - compatible = "ti,omap4-mcspi"; > - reg = <0x48098000 0x200>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "mcspi1"; > - ti,spi-num-cs = <4>; > - dmas = <&sdma 35>, > - <&sdma 36>, > - <&sdma 37>, > - <&sdma 38>, > - <&sdma 39>, > - <&sdma 40>, > - <&sdma 41>, > - <&sdma 42>; > - dma-names = "tx0", "rx0", "tx1", "rx1", > - "tx2", "rx2", "tx3", "rx3"; > - }; > - > - mcspi2: spi@4809a000 { > - compatible = "ti,omap4-mcspi"; > - reg = <0x4809a000 0x200>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "mcspi2"; > - ti,spi-num-cs = <2>; > - dmas = <&sdma 43>, > - <&sdma 44>, > - <&sdma 45>, > - <&sdma 46>; > - dma-names = "tx0", "rx0", "tx1", "rx1"; > - }; > - > - mcspi3: spi@480b8000 { > - compatible = "ti,omap4-mcspi"; > - reg = <0x480b8000 0x200>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "mcspi3"; > - ti,spi-num-cs = <2>; > - dmas = <&sdma 15>, <&sdma 16>; > - dma-names = "tx0", "rx0"; > - }; > - > - mcspi4: spi@480ba000 { > - compatible = "ti,omap4-mcspi"; > - reg = <0x480ba000 0x200>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <0>; > - ti,hwmods = "mcspi4"; > - ti,spi-num-cs = <1>; > - dmas = <&sdma 70>, <&sdma 71>; > - dma-names = "tx0", "rx0"; > - }; > - > - uart1: serial@4806a000 { > - compatible = "ti,omap4-uart"; > - reg = <0x4806a000 0x100>; > - interrupts = ; > - ti,hwmods = "uart1"; > - clock-frequency = <48000000>; > - }; > - > - uart2: serial@4806c000 { > - compatible = "ti,omap4-uart"; > - reg = <0x4806c000 0x100>; > - interrupts = ; > - ti,hwmods = "uart2"; > - clock-frequency = <48000000>; > - }; > - > - uart3: serial@48020000 { > - compatible = "ti,omap4-uart"; > - reg = <0x48020000 0x100>; > - interrupts = ; > - ti,hwmods = "uart3"; > - clock-frequency = <48000000>; > - }; > - > - uart4: serial@4806e000 { > - compatible = "ti,omap4-uart"; > - reg = <0x4806e000 0x100>; > - interrupts = ; > - ti,hwmods = "uart4"; > - clock-frequency = <48000000>; > - }; > - > - uart5: serial@48066000 { > - compatible = "ti,omap4-uart"; > - reg = <0x48066000 0x100>; > - interrupts = ; > - ti,hwmods = "uart5"; > - clock-frequency = <48000000>; > - }; > - > - uart6: serial@48068000 { > - compatible = "ti,omap4-uart"; > - reg = <0x48068000 0x100>; > - interrupts = ; > - ti,hwmods = "uart6"; > - clock-frequency = <48000000>; > - }; > - > - mmc1: mmc@4809c000 { > - compatible = "ti,omap4-hsmmc"; > - reg = <0x4809c000 0x400>; > - interrupts = ; > - ti,hwmods = "mmc1"; > - ti,dual-volt; > - ti,needs-special-reset; > - dmas = <&sdma 61>, <&sdma 62>; > - dma-names = "tx", "rx"; > - pbias-supply = <&pbias_mmc_reg>; > - }; > - > - mmc2: mmc@480b4000 { > - compatible = "ti,omap4-hsmmc"; > - reg = <0x480b4000 0x400>; > - interrupts = ; > - ti,hwmods = "mmc2"; > - ti,needs-special-reset; > - dmas = <&sdma 47>, <&sdma 48>; > - dma-names = "tx", "rx"; > - }; > - > - mmc3: mmc@480ad000 { > - compatible = "ti,omap4-hsmmc"; > - reg = <0x480ad000 0x400>; > - interrupts = ; > - ti,hwmods = "mmc3"; > - ti,needs-special-reset; > - dmas = <&sdma 77>, <&sdma 78>; > - dma-names = "tx", "rx"; > - }; > - > - mmc4: mmc@480d1000 { > - compatible = "ti,omap4-hsmmc"; > - reg = <0x480d1000 0x400>; > - interrupts = ; > - ti,hwmods = "mmc4"; > - ti,needs-special-reset; > - dmas = <&sdma 57>, <&sdma 58>; > - dma-names = "tx", "rx"; > - }; > - > - mmc5: mmc@480d5000 { > - compatible = "ti,omap4-hsmmc"; > - reg = <0x480d5000 0x400>; > - interrupts = ; > - ti,hwmods = "mmc5"; > - ti,needs-special-reset; > - dmas = <&sdma 59>, <&sdma 60>; > - dma-names = "tx", "rx"; > - }; > - > mmu_dsp: mmu@4a066000 { > compatible = "ti,omap4-iommu"; > reg = <0x4a066000 0x100>; > @@ -679,12 +202,6 @@ > ti,iommu-bus-err-back; > }; > > - keypad: keypad@4ae1c000 { > - compatible = "ti,omap4-keypad"; > - reg = <0x4ae1c000 0x400>; > - ti,hwmods = "kbd"; > - }; > - > mcpdm: mcpdm@40132000 { > compatible = "ti,omap4-mcpdm"; > reg = <0x40132000 0x7f>, /* MPU private access */ > @@ -755,55 +272,6 @@ > status = "disabled"; > }; > > - mailbox: mailbox@4a0f4000 { > - compatible = "ti,omap4-mailbox"; > - reg = <0x4a0f4000 0x200>; > - interrupts = ; > - ti,hwmods = "mailbox"; > - #mbox-cells = <1>; > - ti,mbox-num-users = <3>; > - ti,mbox-num-fifos = <8>; > - mbox_ipu: mbox_ipu { > - ti,mbox-tx = <0 0 0>; > - ti,mbox-rx = <1 0 0>; > - }; > - mbox_dsp: mbox_dsp { > - ti,mbox-tx = <3 0 0>; > - ti,mbox-rx = <2 0 0>; > - }; > - }; > - > - timer1: timer@4ae18000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x4ae18000 0x80>; > - interrupts = ; > - ti,hwmods = "timer1"; > - ti,timer-alwon; > - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; > - clock-names = "fck"; > - }; > - > - timer2: timer@48032000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x48032000 0x80>; > - interrupts = ; > - ti,hwmods = "timer2"; > - }; > - > - timer3: timer@48034000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x48034000 0x80>; > - interrupts = ; > - ti,hwmods = "timer3"; > - }; > - > - timer4: timer@48036000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x48036000 0x80>; > - interrupts = ; > - ti,hwmods = "timer4"; > - }; > - > timer5: timer@40138000 { > compatible = "ti,omap5430-timer"; > reg = <0x40138000 0x80>, > @@ -843,37 +311,6 @@ > ti,timer-pwm; > }; > > - timer9: timer@4803e000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x4803e000 0x80>; > - interrupts = ; > - ti,hwmods = "timer9"; > - ti,timer-pwm; > - }; > - > - timer10: timer@48086000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x48086000 0x80>; > - interrupts = ; > - ti,hwmods = "timer10"; > - ti,timer-pwm; > - }; > - > - timer11: timer@48088000 { > - compatible = "ti,omap5430-timer"; > - reg = <0x48088000 0x80>; > - interrupts = ; > - ti,hwmods = "timer11"; > - ti,timer-pwm; > - }; > - > - wdt2: wdt@4ae14000 { > - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; > - reg = <0x4ae14000 0x80>; > - interrupts = ; > - ti,hwmods = "wd_timer2"; > - }; > - > dmm@4e000000 { > compatible = "ti,omap5-dmm"; > reg = <0x4e000000 0x800>; > @@ -905,99 +342,6 @@ > hw-caps-temp-alert; > }; > > - usb3: omap_dwc3@4a020000 { > - compatible = "ti,dwc3"; > - ti,hwmods = "usb_otg_ss"; > - reg = <0x4a020000 0x10000>; > - interrupts = ; > - #address-cells = <1>; > - #size-cells = <1>; > - utmi-mode = <2>; > - ranges; > - dwc3: dwc3@4a030000 { > - compatible = "snps,dwc3"; > - reg = <0x4a030000 0x10000>; > - interrupts = , > - , > - ; > - interrupt-names = "peripheral", > - "host", > - "otg"; > - phys = <&usb2_phy>, <&usb3_phy>; > - phy-names = "usb2-phy", "usb3-phy"; > - dr_mode = "peripheral"; > - }; > - }; > - > - ocp2scp@4a080000 { > - compatible = "ti,omap-ocp2scp"; > - #address-cells = <1>; > - #size-cells = <1>; > - reg = <0x4a080000 0x20>; > - ranges; > - ti,hwmods = "ocp2scp1"; > - usb2_phy: usb2phy@4a084000 { > - compatible = "ti,omap-usb2"; > - reg = <0x4a084000 0x7c>; > - syscon-phy-power = <&scm_conf 0x300>; > - clocks = <&usb_phy_cm_clk32k>, > - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; > - clock-names = "wkupclk", "refclk"; > - #phy-cells = <0>; > - }; > - > - usb3_phy: usb3phy@4a084400 { > - compatible = "ti,omap-usb3"; > - reg = <0x4a084400 0x80>, > - <0x4a084800 0x64>, > - <0x4a084c00 0x40>; > - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > - syscon-phy-power = <&scm_conf 0x370>; > - clocks = <&usb_phy_cm_clk32k>, > - <&sys_clkin>, > - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; > - clock-names = "wkupclk", > - "sysclk", > - "refclk"; > - #phy-cells = <0>; > - }; > - }; > - > - usbhstll: usbhstll@4a062000 { > - compatible = "ti,usbhs-tll"; > - reg = <0x4a062000 0x1000>; > - interrupts = ; > - ti,hwmods = "usb_tll_hs"; > - }; > - > - usbhshost: usbhshost@4a064000 { > - compatible = "ti,usbhs-host"; > - reg = <0x4a064000 0x800>; > - ti,hwmods = "usb_host_hs"; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges; > - clocks = <&l3init_60m_fclk>, > - <&xclk60mhsp1_ck>, > - <&xclk60mhsp2_ck>; > - clock-names = "refclk_60m_int", > - "refclk_60m_ext_p1", > - "refclk_60m_ext_p2"; > - > - usbhsohci: ohci@4a064800 { > - compatible = "ti,ohci-omap3"; > - reg = <0x4a064800 0x400>; > - interrupts = ; > - remote-wakeup-connected; > - }; > - > - usbhsehci: ehci@4a064c00 { > - compatible = "ti,ehci-omap"; > - reg = <0x4a064c00 0x400>; > - interrupts = ; > - }; > - }; > - > bandgap: bandgap@4a0021e0 { > reg = <0x4a0021e0 0xc > 0x4a00232c 0xc > @@ -1010,27 +354,6 @@ > }; > > /* OCP2SCP3 */ > - ocp2scp@4a090000 { > - compatible = "ti,omap-ocp2scp"; > - #address-cells = <1>; > - #size-cells = <1>; > - reg = <0x4a090000 0x20>; > - ranges; > - ti,hwmods = "ocp2scp3"; > - sata_phy: phy@4a096000 { > - compatible = "ti,phy-pipe3-sata"; > - reg = <0x4A096000 0x80>, /* phy_rx */ > - <0x4A096400 0x64>, /* phy_tx */ > - <0x4A096800 0x40>; /* pll_ctrl */ > - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; > - syscon-phy-power = <&scm_conf 0x374>; > - clocks = <&sys_clkin>, > - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; > - clock-names = "sysclk", "refclk"; > - #phy-cells = <0>; > - }; > - }; > - > sata: sata@4a141100 { > compatible = "snps,dwc-ahci"; > reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; > @@ -1184,6 +507,7 @@ > coefficients = <65 (-1791)>; > }; > > +#include "omap5-l4.dtsi" > #include "omap54xx-clocks.dtsi" > > &gpu_thermal { > - Péter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki