Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp2058330imu; Wed, 12 Dec 2018 08:50:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xiqs9x2rf7g0CiKR5gcmWMBLr9DZAo3/u2XpoQKXPfFJL/JE7g7K7EB0fNmbsK8+zSDeWQ X-Received: by 2002:a17:902:bd0b:: with SMTP id p11mr20654748pls.259.1544633403716; Wed, 12 Dec 2018 08:50:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544633403; cv=none; d=google.com; s=arc-20160816; b=u18ftWeJYlsl8itPrrmeaY+2kCFw+ALK6P1y6K9vdAVWnAFUVN7ywrn9ATfnga56NN 0YP9sSfnMD7RXBSeT/NVPuj59tCdJZBoXKEQLMRm4qh+bsRtMVgYteIUQrVxVVNRoOhu 0/OxhCyssl13/8tW1FT+enmMi79u+3znaZ2hLNYdjJMmIz/jeyLlw9fl/Wxqi9EEPnr4 B3ANmwz5/+2Iv39fjTg9fc/Tb+Wc+Do4iPnIibNmxcAwhEqo7VJe3aLXJRS+D3v0S7Ad 95bwzvbr21cDc2Kcv38lX7m2TIkrGhJhmCikFgwxCSnwqnPxaUGtngYESj6MU/+c9bGM NA6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=sfXIFid9lkMuz8Tr7yF6pWr6HFNXLjvlaJWuadL8Ae8=; b=kUpVFVDdXcpdUKIAprhP4SrWZzKXq+YzEaDaXD/MeHcZPmVFu8qUmF3ly03qOnE37E TGBxYNYk1/Kj0Io8RSzEi5dv1iA4sqY429QZ03KvQjnST3amNgxel1DTvPS1PboT7o5Y 0UTo6njs+p8ET8jZneKx9ZsRcdKgn08QeG1IjGjON58AtjxlaUwlT08cBKjVR2cw2DMf PzIaVf5HpK77pEUTaDU3ANoDdTlVBBWSxRgxumjB8BEGMm+pU3kh/ZrS9+txh5iEzdt/ xq5HuE+qWAi+Suxhhuk4F2EdFmyL6SW9rryaq1I4KllfyicIZAfmqBwzfERKFIyW2BD2 5F5Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id az11si14933582plb.386.2018.12.12.08.49.48; Wed, 12 Dec 2018 08:50:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728115AbeLLQsb (ORCPT + 99 others); Wed, 12 Dec 2018 11:48:31 -0500 Received: from foss.arm.com ([217.140.101.70]:44664 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728101AbeLLQs1 (ORCPT ); Wed, 12 Dec 2018 11:48:27 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9107E80D; Wed, 12 Dec 2018 08:48:27 -0800 (PST) Received: from e112298-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 97EBC3F575; Wed, 12 Dec 2018 08:48:25 -0800 (PST) From: Julien Thierry To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, Julien Thierry Subject: [PATCH v7 17/25] arm64: gic-v3: Implement arch support for priority masking Date: Wed, 12 Dec 2018 16:47:17 +0000 Message-Id: <1544633245-6036-18-git-send-email-julien.thierry@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1544633245-6036-1-git-send-email-julien.thierry@arm.com> References: <1544633245-6036-1-git-send-email-julien.thierry@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement architecture specific primitive allowing the GICv3 driver to use priorities to mask interrupts. Signed-off-by: Julien Thierry Suggested-by: Daniel Thompson Cc: Marc Zyngier Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/include/asm/arch_gicv3.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h index b5f8142..14b41dd 100644 --- a/arch/arm64/include/asm/arch_gicv3.h +++ b/arch/arm64/include/asm/arch_gicv3.h @@ -22,6 +22,7 @@ #ifndef __ASSEMBLY__ +#include #include #include #include @@ -162,14 +163,13 @@ static inline bool gic_prio_masking_enabled(void) static inline void gic_pmr_mask_irqs(void) { - /* Should not get called yet. */ - WARN_ON_ONCE(true); + BUILD_BUG_ON(GICD_INT_DEF_PRI <= GIC_PRIO_IRQOFF); + gic_write_pmr(GIC_PRIO_IRQOFF); } static inline void gic_arch_enable_irqs(void) { - /* Should not get called yet. */ - WARN_ON_ONCE(true); + asm volatile ("msr daifclr, #2" : : : "memory"); } #endif /* __ASSEMBLY__ */ -- 1.9.1