Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp171454imu; Wed, 12 Dec 2018 14:22:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/VRJ1nhxILmM/A/kRn1dVCPMR+Xx4WEayjHo+SRzTY39EUYyud9Dn0rpdrCWvV8EZJZVPOk X-Received: by 2002:a63:e156:: with SMTP id h22mr19952588pgk.255.1544653324086; Wed, 12 Dec 2018 14:22:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544653324; cv=none; d=google.com; s=arc-20160816; b=obOg+4uzxXxEwl+81Y55Ce5Xt+7ZNn3uMvPPqkGqXpD/Jc3d+iDyB86xGyzwIIzcRr m2b74SOLjWvLU1fLB0OcXzSyT5rtxOOEooUSbt0cqsjuHo+16yX2fo+/q0oq1RbK7i2H YJ7airQGyvR2JCxUCFQhsXQdlPx8dlrLxIJA7i2KDz/wyM9gGFsFK6022kDEHkgt+Sog WhUqPwtmQZGcB+jXaAEZDzMFwUatKSYUNGWRNDlkjNxWJkpyI+MkF9i8V7alYaj4q8kZ SfEkKHNXsIPflvNs8ayuHM/spJuBXTOQLLf5GmnV08Ci5fSC+wnrRPc9Fej/JLzXqdA1 Y0/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:message-id:date:subject:cc :to:from; bh=TJOhGzIlzuaZqrJA9gEl7GkZSxKqpJ8OfjnN5JlUsb0=; b=blXhI3mnqGgdaTiwEjWWbKSiaTQYsanfCc+zv5FurCAMDcJK8TqCTCT+wPDeeoPH6i eifBfPUP6uR2GeEnYhZ7iMmPBo49c9deUGxIXHtbpH3p5LtkhkckpQJDxE23xHOX1Kn0 SuE3bxOaTYtQgmswYzDt+4L4JHqfzxoc8nHNVGH+/olnNCwku3n1A3B0tjTqHM8crCHz GVc92PYbFOJLWeVuvaRCNs9tJTII6RJgKeu5MlpvwnUOfSB6m8cREVudeUysK9CI+nvd cWxBb5ooTKGjSblxxPR49G8OVwEPHmZRfKJIYl8uD+8I60aio/LXuE7Wtjyxs+/B1Frl ftHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=G5XhvwpH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a20si9824pfh.163.2018.12.12.14.21.49; Wed, 12 Dec 2018 14:22:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=G5XhvwpH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728573AbeLLWQn (ORCPT + 99 others); Wed, 12 Dec 2018 17:16:43 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:40646 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728463AbeLLWQm (ORCPT ); Wed, 12 Dec 2018 17:16:42 -0500 From: Paul Cercueil To: Thierry Reding , Rob Herring , Mark Rutland , Daniel Lezcano , Thomas Gleixner , Ralf Baechle , Paul Burton , James Hogan , Jonathan Corbet Cc: Mathieu Malaterre , Ezequiel Garcia , PrasannaKumar Muralidharan , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-mips@vger.kernel.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org, od@zcrc.me Subject: [PATCH v8 00/26] Ingenic TCU patchset v8 Date: Wed, 12 Dec 2018 23:08:55 +0100 Message-Id: <20181212220922.18759-1-paul@crapouillou.net> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1544652572; bh=TJOhGzIlzuaZqrJA9gEl7GkZSxKqpJ8OfjnN5JlUsb0=; h=From:To:Cc:Subject:Date:Message-Id; b=G5XhvwpH0M9UajYKH7j3MtZoT/E9oDN4rjx5WBzI7k+AUBWU09nqLKiWD/u+gPrzia9lbB0ccCTP19DTUAaM9RU/lFJzbljTsgspYt+Y/QxhkON/wzdKdFFW9em1KiPyLXYKKRj8INEIGP9hCraiES5sgeQs3HQwhHbn5QFNfPw= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Here's the version 8 and hopefully final version of my patchset, which adds support for the Timer/Counter Unit found in JZ47xx SoCs from Ingenic. The big change is that the timer driver has been simplified. The code to dynamically update the system timer or clocksource to a new channel has been removed. Now, the system timer and clocksource are provided as children nodes in the devicetree, and the TCU channel to use for these is deduced from their respective memory resource. The PWM driver will also deduce from its memory resources whether a given PWM channel can be used, or is reserved for the system timers. Kind regards, - Paul Cercueil