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[209.132.180.67]) by mx.google.com with ESMTP id y13si848218pgj.157.2018.12.12.22.19.30; Wed, 12 Dec 2018 22:19:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726977AbeLMGSY (ORCPT + 99 others); Thu, 13 Dec 2018 01:18:24 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:16863 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726542AbeLMGSX (ORCPT ); Thu, 13 Dec 2018 01:18:23 -0500 X-UUID: d1fdeb27563348d39f8cfa10bac8a64a-20181213 X-UUID: d1fdeb27563348d39f8cfa10bac8a64a-20181213 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 661874654; Thu, 13 Dec 2018 14:18:13 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 14:18:07 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 14:18:07 +0800 Message-ID: <1544681887.32198.1.camel@mtksdaap41> Subject: Re: [PATCH v5 2/2] arm: dts: mt2712: add uart APDMA to device tree From: Yingjoe Chen To: Long Cheng CC: Vinod Koul , Rob Herring , "Mark Rutland" , Ryder Lee , "Matthias Brugger" , Dan Williams , Greg Kroah-Hartman , Jiri Slaby , Sean Wang , Sean Wang , , , , , , , , YT Shen Date: Thu, 13 Dec 2018 14:18:07 +0800 In-Reply-To: <1544506645-27979-3-git-send-email-long.cheng@mediatek.com> References: <1544506645-27979-1-git-send-email-long.cheng@mediatek.com> <1544506645-27979-3-git-send-email-long.cheng@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-12-11 at 13:37 +0800, Long Cheng wrote: > 1. add uart APDMA controller device node > 2. add uart 0/1/2/3/4/5 DMA function > > Signed-off-by: Long Cheng > --- > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 50 +++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > index 976d92a..a59728b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > @@ -300,6 +300,9 @@ > interrupts = ; > clocks = <&baud_clk>, <&sys_clk>; > clock-names = "baud", "bus"; > + dmas = <&apdma 10 > + &apdma 11>; > + dma-names = "tx", "rx"; > status = "disabled"; > }; > > @@ -378,6 +381,38 @@ > status = "disabled"; > }; > > + apdma: dma-controller@11000400 { > + compatible = "mediatek,mt2712-uart-dma", > + "mediatek,mt6577-uart-dma"; Sorting, please make sure this is before auxadc: adc@11001000 { > + reg = <0 0x11000400 0 0x80>, > + <0 0x11000480 0 0x80>, > + <0 0x11000500 0 0x80>, > + <0 0x11000580 0 0x80>, > + <0 0x11000600 0 0x80>, > + <0 0x11000680 0 0x80>, > + <0 0x11000700 0 0x80>, > + <0 0x11000780 0 0x80>, > + <0 0x11000800 0 0x80>, > + <0 0x11000880 0 0x80>, > + <0 0x11000900 0 0x80>, > + <0 0x11000980 0 0x80>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&pericfg CLK_PERI_AP_DMA>; > + clock-names = "apdma"; > + #dma-cells = <1>; > + }; > + > uart0: serial@11002000 { > compatible = "mediatek,mt2712-uart", > "mediatek,mt6577-uart"; > @@ -385,6 +420,9 @@ ...deleted