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[209.132.180.67]) by mx.google.com with ESMTP id 9si2748024pfq.129.2018.12.13.15.17.36; Thu, 13 Dec 2018 15:17:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=cj9YYHeg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728868AbeLMXPK (ORCPT + 99 others); Thu, 13 Dec 2018 18:15:10 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:15458 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727928AbeLMXOx (ORCPT ); Thu, 13 Dec 2018 18:14:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1544742896; x=1576278896; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BHWX4R4PvQqPuiagEVF3DBhfwi4Xf90NcYD4tNuJ0oY=; b=cj9YYHegmMS0fKsBSJC5NjLxA82BcDORRr2CNoeoumpUTvdzmmPpIMKO B67nq0qogSlTQtt8b9lYHQeJrA2FXBddBnLmDW41Y0r8j31c240A52ha/ BPsXGsy/yAVGsIi25HWhVBJMZ5q7sg41IJGP8yMHeSHvp27VDXhofV6i3 Jo1Op7DjQBblo9D6nT8i3H/vsbtMdFhl/U+/ouQPN56x5AzRUac67B/1S 2STUjlRUQ7iyEl08iHjCOovTJYKXaKpr04lHfZTBqigx7shnWhTkoN3RA CaxthHKU15ZdaeqEFnYGyqFxM6Zv8cxtT0s49NUVwsvnIwrTUEG+ndYvh g==; X-IronPort-AV: E=Sophos;i="5.56,350,1539619200"; d="scan'208";a="194445539" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Dec 2018 07:14:56 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 13 Dec 2018 14:57:21 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:54 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Daniel Lezcano , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal , Christoph Hellwig Subject: [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Date: Thu, 13 Dec 2018 15:14:28 -0800 Message-Id: <1544742869-19980-4-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> References: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is only one clocksource in RISC-V. The boot cpu initializes that clocksource. No need to keep a percpu data structure. Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt --- drivers/clocksource/riscv_timer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 75262409..c9e65086 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -49,7 +49,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) return get_cycles64(); } -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { +static struct clocksource riscv_clocksource = { .name = "riscv_clocksource", .rating = 300, .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), @@ -115,7 +115,6 @@ static void __init riscv_timebase_frequency(struct device_node *node, static int __init riscv_timer_init_dt(struct device_node *n) { int cpuid, hartid, error; - struct clocksource *cs; hartid = riscv_of_processor_hartid(n); cpuid = riscv_hartid_to_cpuid(hartid); @@ -125,8 +124,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) return 0; /* This should be called only for boot cpu */ - cs = per_cpu_ptr(&riscv_clocksource, cpuid); - clocksource_register_hz(cs, riscv_timebase); + clocksource_register_hz(&riscv_clocksource, riscv_timebase); error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", -- 2.7.4