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[209.132.180.67]) by mx.google.com with ESMTP id e11si2897674pgf.450.2018.12.13.17.40.18; Thu, 13 Dec 2018 17:40:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=aCnnKHO8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728987AbeLNBjY (ORCPT + 99 others); Thu, 13 Dec 2018 20:39:24 -0500 Received: from mail.kernel.org ([198.145.29.99]:34720 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728203AbeLNBjY (ORCPT ); Thu, 13 Dec 2018 20:39:24 -0500 Received: from localhost (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 795A220811; Fri, 14 Dec 2018 01:39:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1544751563; bh=OY7VzTFnl/o7Zj5mlJ2aBunXOzfDB/fOVSpzIQUoHkY=; h=In-Reply-To:Subject:To:References:From:Cc:Date:From; b=aCnnKHO8xtTgxe0yGbrerK54ciPcgG4eQUMM6YGQehYjuaNVcBoZV+b97sAl45u1r 7CRGT/TrvrJfawF5fKmqPXvX0GFwXewDKX8P4NahT5XLrr/hNS1TJlKS8TokblDUM/ ftoDKtw+5JGCKoK3oAvcIrotAz8VyTNl5Ji3Ip9s= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20181208152954.596529f8@archlinux> Subject: Re: [PATCH 1/2] staging: iio: adc: ad7192: Add clock for external clock reference To: Jonathan Cameron , Mircea Caprioru References: <20181206091052.7644-1-mircea.caprioru@analog.com> <20181208152954.596529f8@archlinux> Message-ID: <154475156267.19322.6284056396098102605@swboyd.mtv.corp.google.com> From: Stephen Boyd User-Agent: alot/0.8 Cc: Michael.Hennerich@analog.com, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devel@driverdev.osuosl.org, Rob Herring , linux-clk@vger.kernel.org Date: Thu, 13 Dec 2018 17:39:22 -0800 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Jonathan Cameron (2018-12-08 07:29:54) > On Thu, 6 Dec 2018 11:10:51 +0200 > Mircea Caprioru wrote: >=20 > > This patch adds a clock to the state structure of ad7192 for getting the > > external clock frequency. This modifications is in accordance with clock > > framework dt bindings documentation. > >=20 > > Signed-off-by: Mircea Caprioru >=20 > +cc Rob and the clk list for advise on how to do the binding for this one. >=20 > It is basically 2 pins, you can put a clock in on one of them or connect > a crystal across them. The driver has to set a register to say which is > the case. =20 >=20 > Current proposal is two optional clocks (fall back to internal oscillator) > but that doesn't seem to be commonly done, so I'm wondering if there > is a 'standard' way to handle this sort of thing. >=20 I'm not sure I fully understand, but I think perhaps assigned-clock-parents would work? Or does that not work because either way some parent is assigned, either the crystal or the optional clk that isn't a crystal?