Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp2707898imu; Mon, 17 Dec 2018 06:36:04 -0800 (PST) X-Google-Smtp-Source: AFSGD/XmVSY9bh4nD+OS9jfGw7qMLKQct8H/sNXazyOKtsLeM1AicFuubvNSoK5ibMn2HKZxr7w3 X-Received: by 2002:a63:bd1a:: with SMTP id a26mr12192037pgf.121.1545057364596; Mon, 17 Dec 2018 06:36:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545057364; cv=none; d=google.com; s=arc-20160816; b=tmVleGePabxLzi7KSR5ynhBLJ5G+MaUPKyB8Rop3mzQ+v9ktVhYd3cl59knWHcYxUw WD6KxYVud8wbORjXihSV857+Tjau0opn5F6CYkTvf6DO6sQAUE99s7gRYDXTNlnSoXNz RcxfIIQP6WdBILekjjaJctGEkImZhBYT0VhgJS9mGIb0HzvRWn2kEsFph640LgL9D5yn 3kzZjuGOwXArcdZq227eBJ4NjPYILiY0m6So1PSLUOiHg2YpDz/J+PcqNAqqyq4fYpDL KvQjqunTuT3mZCt0siqNK3Ir/BPmYhNrLyti8mJUw0S629/kF9bE0m5np/biYSOLr/Nh XCmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=sByPFRQdZ3pV2dRM82TBPy4o+IfKHjMdw9AGPyLHOeE=; b=B62qgChMi7DnrWfmbJWQFRAQQiLoCwH8o+daA2zr4hVmqYAYw/o/VCFznoYLCw7My7 7MP8TPmaLW3p4Y0KUhopUelScgTTT5JYg90SNOlUqxgFOOn6h52v44RkkFmPgKLs/vTx HJEPxwb3xUbOnOBxxgEqEQXD29bmSMWlulcka9+TlNYISAZyv7Dhj87pPBuHlAJlOOsS DJyH7M1up+u7Arh5hi14T3iI6srBVLN/lCzDTRAK377FcgOET5x+unXRNCSpHtEa2ImT pEURs85ua4/cgA7sDpS4oDVWKSg0weRb6FYDyuvlWTkmqmY5H9+UXtDMRsxWqQ2rS48m /V+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ba9si9112932plb.109.2018.12.17.06.35.47; Mon, 17 Dec 2018 06:36:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732060AbeLQOXF (ORCPT + 99 others); Mon, 17 Dec 2018 09:23:05 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:29770 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731916AbeLQOXC (ORCPT ); Mon, 17 Dec 2018 09:23:02 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id wBHELmjt018492; Mon, 17 Dec 2018 15:22:34 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2pcr8xjc8r-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 17 Dec 2018 15:22:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CE5DC31; Mon, 17 Dec 2018 14:22:32 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A26022424; Mon, 17 Dec 2018 14:22:32 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 17 Dec 2018 15:22:32 +0100 Received: from localhost (10.201.20.122) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 17 Dec 2018 15:22:31 +0100 From: Benjamin Gaignard To: , , , , , CC: , , , , Benjamin Gaignard Subject: [PATCH v3 0/3] Make STM32 interrupt controller use hwspinlock Date: Mon, 17 Dec 2018 15:22:12 +0100 Message-ID: <20181217142215.17493-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.20.122] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-12-17_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series allow to protect STM32 interrupt controller configuration registers with a hwspinlock to avoid conflicting accesses between processors. version 3: - with bindings patch version 2: - rework hwspinlock locking sequence in stm32 irqchip to take care of the cases where hwspinlock node is disabled or not yet probed Benjamin Gaignard (3): dt-bindings: interrupt-controller: stm32: Document hwlock properties irqchip: stm32: protect configuration registers with hwspinlock ARM: dts: stm32: Add hwlock for irqchip on stm32mp157 .../interrupt-controller/st,stm32-exti.txt | 4 + arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/irqchip/irq-stm32-exti.c | 116 ++++++++++++++++++--- 3 files changed, 105 insertions(+), 16 deletions(-) -- 2.15.0