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Date:   Tue, 18 Dec 2018 03:13:47 +0200
From:   Aaro Koskinen <aaro.koskinen@iki.fi>
To:     "Maciej W. Rozycki" <macro@linux-mips.org>
Cc:     Rich Felker <dalias@libc.org>, Andy Lutomirski <luto@kernel.org>,
        Linux MIPS Mailing List <linux-mips@linux-mips.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Paul Burton <paul.burton@imgtec.com>,
        David Daney <david.daney@cavium.com>,
        Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <paul.burton@mips.com>,
        James Hogan <jhogan@kernel.org>
Subject: Re: Fixing MIPS delay slot emulation weakness?
Message-ID: <20181218011346.GA26211@darkstar.musicnaut.iki.fi>
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Hi,

On Mon, Dec 17, 2018 at 01:55:28AM +0000, Maciej W. Rozycki wrote:
>  As to actual implementations I believe all the Cavium Octeon line CPUs 
> (David, please correct me if I am wrong) have no FPU and they have vendor 
> extensions beyond the base ISA + ASE instruction set.  Arguably you could 
> say that their additional instructions should not be scheduled into FPU 
> branch delay slots then, however the toolchain will happily do that, as I 
> wrote before.

Octeon III added/introduced FPU.

A.