Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp3753965imu; Tue, 18 Dec 2018 03:42:44 -0800 (PST) X-Google-Smtp-Source: AFSGD/X+IUw6TrPBllhzexlUfWdDmQHbtnpd/2PNC4aF26r2qMuDXz/Oo0EhTXtyNwTBFe6bEZ30 X-Received: by 2002:a63:f30d:: with SMTP id l13mr15608262pgh.399.1545133364795; Tue, 18 Dec 2018 03:42:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545133364; cv=none; d=google.com; s=arc-20160816; b=bOPxZPVVSP4uewsoEAW2Y50isDYdZI8Vo7pCeyUSpnH9WURAy7E7zBHF1NeCpPaBUv sBYOz1WgOx8JK/ZBIDefHfR3vlyu7wQwt5moZedk2O5vnVYymQ6thcPMci7/KiVCMobY xnMfysjlswrSjhLGTX88iDiiv3BF2w55R7b+11I3MoFA2Trq0Zpp8LcuBfCCs3m86cEC COHmgipBGLmaCbQWU/ka9mzos3m066kD3HUdkNjcJqeaEeeLRs/OsotcHJblIQSJMThr 3GKpTD861zdk2BScCRBtsGj7eVvxjRwuOdD91nmXP5mneIwnS9eMXK5GhQqvTK+vbiok dFPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=miByt4UBtujLZ6gakMhRKo706aoBxPu/AGSy/L6iA4Y=; b=nfPPxBJKnKzrX+InA4WcBFNnDzvgDTUulXYezuC5j3giDv/GyPfRzD9N80KT7SP460 Ym8pZ478oWP91NLc9guwdH9Bw/YTglTq7cBFIOcTih4vatuH9C1ybIpSqlRMwnrAY/BA bcS07CTvP73p/Ih/qszCqFAjy5EP0BTODnR3ty2+SWSjLP4fRRnEhKRx/ICRYIhZvkEq 4OXEp7WHDgYhR6yjHkmJ5XAFgseNjrizELAhqjsda+PD5/pFg04zgl1Fxj6ZN4oW/oh7 wtrcHq0p8AWwwJ2a4LD2mHK6MoHwftGkWcKMGMzuaJR2W1AiBKiO6Jw6d0iq+CgpXYHJ lKWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g9si14363495pfd.86.2018.12.18.03.42.29; Tue, 18 Dec 2018 03:42:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726601AbeLRLkj (ORCPT + 99 others); Tue, 18 Dec 2018 06:40:39 -0500 Received: from mga03.intel.com ([134.134.136.65]:62099 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726364AbeLRLkh (ORCPT ); Tue, 18 Dec 2018 06:40:37 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2018 03:40:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,367,1539673200"; d="scan'208";a="304764709" Received: from aubrey-skl.sh.intel.com ([10.239.53.9]) by fmsmga005.fm.intel.com with ESMTP; 18 Dec 2018 03:40:34 -0800 From: Aubrey Li To: tglx@linutronix.de, mingo@redhat.com, peterz@infradead.org, hpa@zytor.com Cc: ak@linux.intel.com, tim.c.chen@linux.intel.com, dave.hansen@intel.com, arjan@linux.intel.com, aubrey.li@intel.com, linux-kernel@vger.kernel.org, Aubrey Li Subject: [PATCH v6 1/3] x86/fpu: track AVX-512 usage of tasks Date: Tue, 18 Dec 2018 12:22:16 +0800 Message-Id: <20181218042218.8653-1-aubrey.li@intel.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org User space tools which do automated task placement need information about AVX-512 usage of tasks, because AVX-512 usage could cause core turbo frequency drop and impact the running task on the sibling CPU. The XSAVE hardware structure has bits that indicate when valid state is present in registers unique to AVX-512 use. Use these bits to indicate when AVX-512 has been in use and add per-task AVX-512 state timestamp tracking to context switch. Well-written AVX-512 applications are expected to clear the AVX-512 state when not actively using AVX-512 registers, so the tracking mechanism is imprecise and can theoretically miss AVX-512 usage during context switch. But it has been measured to be precise enough to be useful under real-world workloads like tensorflow and linpack. If higher precision is required, suggest user space tools to use the PMU-based mechanisms in combination. Signed-off-by: Aubrey Li Cc: Peter Zijlstra Cc: Andi Kleen Cc: Tim Chen Cc: Dave Hansen Cc: Arjan van de Ven --- arch/x86/include/asm/fpu/internal.h | 7 +++++++ arch/x86/include/asm/fpu/types.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h index a38bf5a1e37a..8778ac172255 100644 --- a/arch/x86/include/asm/fpu/internal.h +++ b/arch/x86/include/asm/fpu/internal.h @@ -411,6 +411,13 @@ static inline int copy_fpregs_to_fpstate(struct fpu *fpu) { if (likely(use_xsave())) { copy_xregs_to_kernel(&fpu->state.xsave); + + /* + * AVX512 state is tracked here because its use is + * known to slow the max clock speed of the core. + */ + if (fpu->state.xsave.header.xfeatures & XFEATURE_MASK_AVX512) + fpu->avx512_timestamp = jiffies_64; return 1; } diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h index 202c53918ecf..81393dabdb46 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -302,6 +302,13 @@ struct fpu { */ unsigned char initialized; + /* + * @avx512_timestamp: + * + * Records the timestamp of AVX512 use during last context switch. + */ + u64 avx512_timestamp; + /* * @state: * -- 2.17.1