Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
MIME-Version: 1.0
References: <1545193599-11604-1-git-send-email-hongxing.zhu@nxp.com>
In-Reply-To: <1545193599-11604-1-git-send-email-hongxing.zhu@nxp.com>
From:   Sven Van Asbroeck <thesven73@gmail.com>
Date:   Wed, 19 Dec 2018 10:07:39 -0500
Message-ID: <CAGngYiW5Y9+_kajQHKahUN-vGFoQvuO4-b0nzzCBSAt2TykQDg@mail.gmail.com>
Subject: Re: [v5] PCI: imx: make msi work without CONFIG_PCIEPORTBUS=y
To:     Richard Zhu <hongxing.zhu@nxp.com>
Cc:     "bhelgaas@google.com" <bhelgaas@google.com>,
        "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        "andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

This patch seems to fix the regression on my board: i.MX6 with a
tg3-based pcie NIC:
   CPU identified as i.MX6Q, silicon rev 1.5
   tg3 0000:03:00.0 eth0: Tigon3 [partno(BCM57780) rev 57780001] (PCI Express)

Tested-by: Sven Van Asbroeck <TheSven73@googlemail.com>

On Wed, Dec 19, 2018 at 12:25 AM Richard Zhu <hongxing.zhu@nxp.com> wrote:
>
> Assertion of the MSI Enable bit of RC's MSI CAP is mandatory required to
> trigger MSI on i.MX6 PCIe.
> This bit would be asserted when CONFIG_PCIEPORTBUS=y.
> Thus, the MSI works fine on i.MX6 PCIe before the commit "f3fdfc4".
>
> Assert it unconditionally when MSI is enabled.
> Otherwise, the MSI wouldn't be triggered although the EP is present and
> the MSIs are assigned.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> Changes v1 -> v2:
> * Assert the MSI_EN unconditionally when MSI is supported.
> Changes v2 -> v3:
> * Remove the IS_ENABLED(CONFIG_PCI_MSI) since the driver depends on
> PCI_MSI_IRQ_DOMAIN
> * Extended with a check for pci_msi_enabled() to see if the user
> explicitly want legacy IRQs
> Changes v3 -> v4:
> * Refer to Bjorn's comments, refine the subject and commit log and change
> the PCI_MSI_CAP to PCIE_RC_IMX6_MSI_CAP.
> Changes v4 -> v5:
> * Correct one spell mistake from PCIE_RC_MSI_IMX6_CAP to
> PCIE_RC_IMX6_MSI_CAP.
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index e563ca9..73542dd 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -82,6 +82,7 @@ struct imx6_pcie {
>  #define PHY_PLL_LOCK_WAIT_USLEEP_MAX   200
>
>  /* PCIe Root Complex registers (memory-mapped) */
> +#define PCIE_RC_IMX6_MSI_CAP                   0x50
>  #define PCIE_RC_LCR                            0x7c
>  #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1       0x1
>  #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2       0x2
> @@ -999,6 +1000,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>         struct resource *dbi_base;
>         struct device_node *node = dev->of_node;
>         int ret;
> +       u16 val;
>
>         imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
>         if (!imx6_pcie)
> @@ -1149,6 +1151,14 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>         if (ret < 0)
>                 return ret;
>
> +       if (pci_msi_enabled()) {
> +               val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
> +                               PCI_MSI_FLAGS);
> +               val |= PCI_MSI_FLAGS_ENABLE;
> +               dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
> +                               PCI_MSI_FLAGS, val);
> +       }
> +
>         return 0;
>  }
>
> --
> 2.7.4
>