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From:   "james qian wang (Arm Technology China)" <james.qian.wang@arm.com>
To:     Rob Herring <robh+dt@kernel.org>
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        Linux Doc Mailing List <linux-doc@vger.kernel.org>,
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        dri-devel <dri-devel@lists.freedesktop.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Masahiro Yamada <yamada.masahiro@socionext.com>,
        "Yiqi Kang (Arm Technology China)" <Yiqi.Kang@arm.com>,
        Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
        "Tiannan Zhu (Arm Technology China)" <Tiannan.Zhu@arm.com>,
        Jonathan Corbet <corbet@lwn.net>,
        David Airlie <airlied@linux.ie>,
        Mali DP Maintainers <malidp@foss.arm.com>,
        "thomas Sun (Arm Technology China)" <thomas.Sun@arm.com>,
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        "Julien Yin (Arm Technology China)" <Julien.Yin@arm.com>,
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        David Miller <davem@davemloft.net>
Subject: Re: [PATCH v2 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM
 display processor D71
Thread-Topic: [PATCH v2 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM
 display processor D71
Thread-Index: AQHUl5cAOCEuMH0GRUuCne9wdYhyiw==
Date:   Thu, 20 Dec 2018 10:54:34 +0000
Message-ID: <20181220105419.GA7599@james-ThinkStation-P300>
References: <20181219123147.16090-1-james.qian.wang@arm.com>
 <20181219123147.16090-3-james.qian.wang@arm.com>
 <CAL_JsqLsQ__dpu0Xh5zmLbOx_B8t0t0kJzoh-nOf=nuZSppAYg@mail.gmail.com>
In-Reply-To: <CAL_JsqLsQ__dpu0Xh5zmLbOx_B8t0t0kJzoh-nOf=nuZSppAYg@mail.gmail.com>
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On Wed, Dec 19, 2018 at 07:55:44AM -0600, Rob Herring wrote:
> On Wed, Dec 19, 2018 at 6:33 AM james qian wang (Arm Technology China)
> <james.qian.wang@arm.com> wrote:
> >
> > Add DT bindings documentation for the ARM display processor D71 and lat=
er
> > IPs.
> >
> > Signed-off-by: James (Qian) Wang <james.qian.wang@arm.com>
> > ---
> >  .../bindings/display/arm/arm,komeda.txt       | 87 +++++++++++++++++++
> >  1 file changed, 87 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/display/arm/arm,k=
omeda.txt
> >
> > diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.t=
xt b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
> > new file mode 100644
> > index 000000000000..d4b53c11b2a2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt
> > @@ -0,0 +1,87 @@
> > +Device Tree bindings for ARM Komeda display driver
> > +
> > +Required properties:
> > +- compatible: Should be "arm,mali-d71"
> > +- reg: Physical base address and length of the registers in the system
> > +- interrupts: the interrupt line numbers of the device in the system
>=20
> How many?

Sorry, only one interrupt. will fix it in the next version.=20

> > +- interrupt-names: contains the names of the IRQs in the order they we=
re
> > +    provided in the "interrupts" property. Must contain: "DPU".
>=20
> There's no point in *-names when there is only one entry.
>=20
> > +- clocks: A list of phandle + clock-specifier pairs, one for each entr=
y
> > +    in 'clock-names'
> > +- clock-names: A list of clock names. It should contain:
> > +      - "pclk": for the APB interface clock
> > +      - "mclk": for the main processor clock
>=20
> The order here doesn't match the example.

will fix it.

>=20
> > +- #address-cells: Must be 1
> > +- #size-cells: Must be 0
> > +
> > +Required properties for sub-node: pipeline@nq
> > +Each device contains one or two pipeline sub-nodes (at least one), eac=
h
> > +pipeline node should provide properties:
> > +- reg: Zero-indexed identifier for the pipeline
> > +- clocks: A list of phandle + clock-specifier pairs, one for each entr=
y
> > +    in 'clock-names'
> > +- clock-names: should contain:
> > +      - "aclk": AXI interface clock
> > +      - "pxclk": pixel clock
>=20
> The order here doesn't match the example.
>

will fix it in the next version.

> > +
> > +- port: each pipeline connect to an encoder input port. The connection=
 is
> > +    modelled using the OF graph bindings specified in
>=20
> modeled

will fix it.

>=20
> > +    Documentation/devicetree/bindings/graph.txt
> > +
> > +Optional properties:
> > +  - memory-region: phandle to a node describing memory (see
> > +    Documentation/devicetree/bindings/reserved-memory/reserved-memory.=
txt)
> > +    to be used for the framebuffer; if not present, the framebuffer ma=
y
> > +    be located anywhere in memory.
> > +
> > +Example:
> > +/ {
> > +       ...
> > +
> > +       dp0: display@c00000 {
> > +               #address-cells =3D <1>;
> > +               #size-cells =3D <0>;
> > +               compatible =3D "arm,mali-d71";
> > +               reg =3D <0xc00000 0x20000>;
> > +               interrupts =3D <0 168 4>;
> > +               interrupt-names =3D "DPU";
> > +               clocks =3D <&dpu_mclk>, <&dpu_aclk>;
> > +               clock-names =3D "mclk", "pclk";
> > +
> > +               pl0: pipeline@0 {
> > +                       clocks =3D <&fpgaosc2>, <&dpu_aclk>;
> > +                       clock-names =3D "pxclk", "aclk";
> > +                       reg =3D <0>;
>=20
> Is there a register range for each pipeline? If so, using that here
> would be better than index.

Sorry, there is no register range for the pipeline.

>=20
> > +
> > +                       ports {
> > +                               #address-cells =3D <1>;
> > +                               #size-cells =3D <0>;
> > +
> > +                               port@0 {
> > +                                       reg =3D <0>;
>=20
> You can drop 'ports' moving port up a level. And for a single port,
> you don't need reg.

you're right will fix it.
>=20
> > +                                       dp0_pl0_out: endpoint {
> > +                                               remote-endpoint =3D <&d=
b_dvi0_in>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +               pl1: pipeline@1 {
> > +                       clocks =3D <&fpgaosc2>, <&dpu_aclk>;
> > +                       clock-names =3D "pxclk", "aclk";
> > +                       reg =3D <1>;
> > +
> > +                       ports {
> > +                               #address-cells =3D <1>;
> > +                               #size-cells =3D <0>;
> > +
> > +                               port@0 {
> > +                                       reg =3D <0>;
> > +                                       dp0_pl1_out: endpoint {
> > +                                               remote-endpoint =3D <&d=
b_dvi1_in>;
> > +                                       };
> > +                               };
> > +                       };
> > +               };
> > +       };
> > +       ...
> > +};
> > --
> > 2.17.1
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel