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[209.132.180.67]) by mx.google.com with ESMTP id t136si17717217pfc.262.2018.12.20.09.31.39; Thu, 20 Dec 2018 09:31:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=EqLHNLvl; dkim=pass header.i=@codeaurora.org header.s=default header.b="bh02hd/M"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387741AbeLTRal (ORCPT + 99 others); Thu, 20 Dec 2018 12:30:41 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:35006 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387644AbeLTRai (ORCPT ); Thu, 20 Dec 2018 12:30:38 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 6585F6090C; Thu, 20 Dec 2018 17:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545327037; bh=s/vBiF/stLHSG1XGFLewCr5bYqm7HK5fSuvw7/3Fjs4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EqLHNLvlO3GyCbRJKffpGpq54U6jy3m3kUp9yCfrpYiY9fZNDBmZOEA5/tSZXGADF ycaQsWbp3gRMI1wpioD1GXL719cFX5lt9NC5n5Nf6qoJKJldjhVhuN640jRz6ulcuf ass4eUzkmJM/FK6Y9t9CXzRoz6PA1DHUTasgiBjY= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.0 Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C5CD860886; Thu, 20 Dec 2018 17:30:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1545327036; bh=s/vBiF/stLHSG1XGFLewCr5bYqm7HK5fSuvw7/3Fjs4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bh02hd/MG0MHsSnoii5ZSMacQ/xLMnWRD4qgvzm88HMoEuEYn3ZFhMPq2GhP3Pk3M qYYXIXKtmXGIFiLZXXLpddcyThPPt7N00nNzkJw2VGncLI1xniib0BqX2FjN1rBUqF be3xYXNiMjJvoCEjdJ7QM2Es7CXO9qoO0IxQN+P0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C5CD860886 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, dianders@chromium.org, georgi.djakov@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , Rob Clark , David Airlie , Mark Rutland Subject: [PATCH v3 2/3] dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU Date: Thu, 20 Dec 2018 10:30:25 -0700 Message-Id: <20181220173026.3857-3-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181220173026.3857-1-jcrouse@codeaurora.org> References: <20181220173026.3857-1-jcrouse@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add documentation for the interconnect and interconnect-names bindings for the GPU node as detailed by bindings/interconnect/interconnect.txt. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 9c89f4fdb8ca..5b04393dcb15 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -20,6 +20,8 @@ Required properties: - qcom,adreno-630.2 - iommus: optional phandle to an adreno iommu instance - operating-points-v2: optional phandle to the OPP operating points +- interconnect: optional phandle to a interconnect provider. See + ../interconnect/interconnect.txt for details. - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 @@ -68,6 +70,8 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; + interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; + qcom,gmu = <&gmu>; }; }; -- 2.18.0