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a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oNeKExCutgOK38V9MkPTTIC1w4o2zbdxUb5j/rfZDw0=; b=hbqJ8zUHWTl29ihYL+8LNV7uDSyUhRzbhwgG4wYgYEVExooz/xEWuQgJ7HX67ce74TnH3+bM3m7v/e+bxP1RTcf/3Go8lrhnWxSRvQEDB56SSakx1M/POpgxw/NY12vqNNF0eO0p5DzMY+YDOr8AAuwRMn4eUA0XDIkOLX3/UDI= Received: from AM0PR08MB4483.eurprd08.prod.outlook.com (20.179.35.149) by AM0PR08MB3187.eurprd08.prod.outlook.com (52.134.93.156) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1446.19; Fri, 21 Dec 2018 09:59:12 +0000 Received: from AM0PR08MB4483.eurprd08.prod.outlook.com ([fe80::1dff:434f:5905:45db]) by AM0PR08MB4483.eurprd08.prod.outlook.com ([fe80::1dff:434f:5905:45db%5]) with mapi id 15.20.1446.020; Fri, 21 Dec 2018 09:59:12 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau CC: "Jonathan Chai (Arm Technology China)" , Brian Starkey , "Julien Yin (Arm Technology China)" , "thomas Sun (Arm Technology China)" , Alexandru-Cosmin Gheorghe , "Lowry Li (Arm Technology China)" , Ayan Halder , "Tiannan Zhu (Arm Technology China)" , "Jin Gao (Arm Technology China)" , "Yiqi Kang (Arm Technology China)" , nd , "malidp@foss.arm.com" , "maarten.lankhorst@linux.intel.com" , "maxime.ripard@bootlin.com" , "sean@poorly.run" , "corbet@lwn.net" , "linux-doc@vger.kernel.org" , "rdunlap@infradead.org" , "mchehab+samsung@kernel.org" , "davem@davemloft.net" , "gregkh@linuxfoundation.org" , "akpm@linux-foundation.org" , "nicolas.ferre@microchip.com" , "arnd@arndb.de" , "robh+dt@kernel.org" , Mark Rutland , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "airlied@linux.ie" , "yamada.masahiro@socionext.com" , "james qian wang (Arm Technology China)" Subject: [PATCH v3 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Topic: [PATCH v3 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Index: AQHUmRPTBdPt1uc570uDsKJLIqlNSA== Date: Fri, 21 Dec 2018 09:59:12 +0000 Message-ID: <20181221095757.15510-3-james.qian.wang@arm.com> References: <20181221095757.15510-1-james.qian.wang@arm.com> In-Reply-To: <20181221095757.15510-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SY3PR01CA0099.ausprd01.prod.outlook.com (2603:10c6:0:19::32) To AM0PR08MB4483.eurprd08.prod.outlook.com (2603:10a6:208:145::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=james.qian.wang@arm.com; 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Signed-off-by: James (Qian) Wang Changes in v3: - Deleted unnecessary property: interrupt-names. - Dropped 'ports' and moving 'port' up a level. --- .../bindings/display/arm/arm,komeda.txt | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/arm/arm,komed= a.txt diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.txt b= /Documentation/devicetree/bindings/display/arm/arm,komeda.txt new file mode 100644 index 000000000000..b4e450243c7d --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt @@ -0,0 +1,79 @@ +Device Tree bindings for ARM Komeda display driver + +Required properties: +- compatible: Should be "arm,mali-d71" +- reg: Physical base address and length of the registers in the system +- interrupts: the interrupt line number of the device in the system +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: A list of clock names. It should contain: + - "mclk": for the main processor clock + - "pclk": for the APB interface clock +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Required properties for sub-node: pipeline@nq +Each device contains one or two pipeline sub-nodes (at least one), each +pipeline node should provide properties: +- reg: Zero-indexed identifier for the pipeline +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: should contain: + - "pxclk": pixel clock + - "aclk": AXI interface clock + +- port: each pipeline connect to an encoder input port. The connection is + modeled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt + +Optional properties: + - memory-region: phandle to a node describing memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) + to be used for the framebuffer; if not present, the framebuffer may + be located anywhere in memory. + +Example: +/ { + ... + + dp0: display@c00000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "arm,mali-d71"; + reg =3D <0xc00000 0x20000>; + interrupts =3D <0 168 4>; + clocks =3D <&dpu_mclk>, <&dpu_aclk>; + clock-names =3D "mclk", "pclk"; + + dp0_pipe0: pipeline@0 { + clocks =3D <&fpgaosc2>, <&dpu_aclk>; + clock-names =3D "pxclk", "aclk"; + reg =3D <0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + dp0_pipe0_out: endpoint { + remote-endpoint =3D <&db_dvi0_in>; + }; + }; + }; + + dp0_pipe1: pipeline@1 { + clocks =3D <&fpgaosc2>, <&dpu_aclk>; + clock-names =3D "pxclk", "aclk"; + reg =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + dp0_pipe1_out: endpoint { + remote-endpoint =3D <&db_dvi1_in>; + }; + }; + }; + }; + ... +}; --=20 2.17.1