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[209.132.180.67]) by mx.google.com with ESMTP id f124si23070565pfa.1.2018.12.21.10.33.28; Fri, 21 Dec 2018 10:33:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fWPzdsjz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389046AbeLUJ5R (ORCPT + 99 others); Fri, 21 Dec 2018 04:57:17 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:40647 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388930AbeLUJ5R (ORCPT ); Fri, 21 Dec 2018 04:57:17 -0500 Received: by mail-lj1-f193.google.com with SMTP id n18-v6so4182212lji.7 for ; Fri, 21 Dec 2018 01:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=i7YKGAkjxUIo6TZyT8S5jO0gVM/z67R7qDqWLXKFnOM=; b=fWPzdsjz/d2mgU4kuLHefDE53G7AfoUyzM5X+ZX2hzCzDVzKtEffKJI4rCHcCO0R0n UdadU6wtqP5VWw/hPnLTWzJg/BIG5Q6IFEbmii9XBaxzaYYN46C0lzVSPYdwtTmR7WKF He4P136CL8WTKoj+K3/Z4FEe6oYgpqZL1FWII= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=i7YKGAkjxUIo6TZyT8S5jO0gVM/z67R7qDqWLXKFnOM=; b=e3C7TDF3qwNWb4akcLMfq7foiszYfPpsKtPsAMnDywiCAPFK08Q6K+FxnPvjrHRiES 0AhQfsK+ncpOl9fxyjXnsqyCViKPmcSI69RnYfAqctf33Mfwyei0IykeiX/ZMo/d+Dh5 b8545kAAxW5KpUHcbREXKjmw8AH+VjD4FBvzPlbMM+sjPzVpiU52XpRtSn726EAzB0ld 8NHeLIFotJ7+mDh3tCnqJAgD+f8dhOVRG0LXPK/ZPXGNEg6AYLax899SCGXeB/3E4oxL CM2CM9zfqY3354x9bqm0s6/2QFuEToZXjbgjWJeMdSTrO42n33jOvrBRzuKZExHXc8M0 C5eQ== X-Gm-Message-State: AJcUukeOk1GlDfJUgzSjB8b8KH7LbabJhR47WAXNAJC5fmajy+FcFYHe abxrbuK/pav61cpJpTi1uXbdSRfTwfqNxLabghl8Ow== X-Received: by 2002:a2e:710a:: with SMTP id m10-v6mr1157048ljc.66.1545386235773; Fri, 21 Dec 2018 01:57:15 -0800 (PST) MIME-Version: 1.0 References: <1544615784-29331-1-git-send-email-andrei.stefanescu@microchip.com> <1544615784-29331-3-git-send-email-andrei.stefanescu@microchip.com> In-Reply-To: <1544615784-29331-3-git-send-email-andrei.stefanescu@microchip.com> From: Linus Walleij Date: Fri, 21 Dec 2018 10:57:03 +0100 Message-ID: Subject: Re: [PATCH v4 2/2] gpio: add driver for SAMA5D2 PIOBU pins To: Andrei.Stefanescu@microchip.com Cc: Rob Herring , Greg KH , Nicolas Ferre , Mark Rutland , Ludovic Desroches , Cristian.Birsan@microchip.com, Linux ARM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 12, 2018 at 12:57 PM wrote: > PIOBU pins do not lose their voltage during Backup/Self-refresh. > This patch adds a simple GPIO controller for them and a > maintainer for the driver. > > This driver adds support for using the pins as GPIO > offering the possibility to read/set the voltage. > > Signed-off-by: Andrei Stefanescu Patch applied for v4.21, sorry for taking so long to reply! Good work on this driver Andrei, it looks really nice now. Yours, Linus Walleij