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[209.132.180.67]) by mx.google.com with ESMTP id z12si4978595plk.90.2018.12.23.03.32.42; Sun, 23 Dec 2018 03:32:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=r5QhxR9N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390337AbeLVRHY (ORCPT + 99 others); Sat, 22 Dec 2018 12:07:24 -0500 Received: from mail-ot1-f65.google.com ([209.85.210.65]:40960 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388818AbeLVRHY (ORCPT ); Sat, 22 Dec 2018 12:07:24 -0500 Received: by mail-ot1-f65.google.com with SMTP id u16so7915827otk.8 for ; Sat, 22 Dec 2018 09:07:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=K39DZ/tNuiOgoTKEhunBwHj8o6t9D0Ccp0K9bHFYS2I=; b=r5QhxR9NGhKbvg+vbeKXtr4hERJgX60w0vPTRquSZQjBlaueHqgEISySE9YGy+PqLL I1Jjg3u126vyaa2PNsXsuF1K/edTCfmJpIZZU2QidaY0jKN5G4FotyAxlznyz0bsJ4NH 14TH+UDjWroSO2J9AnwLZVL4IzweIYc5ia+jcJs0c3HNpbbrtCFzGhBaqQgtzFaYhJ3c HViJYjsld+2BK2xNm25nqlZ/x2F4oGvkThJeLCAo56LgjYKuWuVHFtp0jLhMCrvG0V70 HvwXawN8FJsoKOToH8X9oO1rv5D0LjWVKqIQyTa2F9kJHByygK3k8EIUPqcbG7zmGkJV /yXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=K39DZ/tNuiOgoTKEhunBwHj8o6t9D0Ccp0K9bHFYS2I=; b=Od1dM6hL3X8Va5fkqzJjMZ5wVzmFr0ia+5B/AZmQSQaMwVWDnHiKlCi/Lzy5qDS8of jAshXlGS7UW24gYGmP7etS2HdcPJGGgxsv/DiEWMVVO4aeac2BJYQ0pvWR4mTtYIGCcD RANeBs8hDJsaP1Btpk9YBsEUCUmUgyr86rAzGcv7qiINW5GaTpAIO4jNSZ4VVpgmVR56 VfFS30ob/0Tn88v3AvkkmL6jnW9MHCoS6Lux/hdC4ZLMzCMAlTXilg55FjCviL7FUzCn K1EiisfDc7tXGUBXf4ww7uqlScwYBMD4EmzoLzGAWOjKiDQaPrV7wXb0EWzNoYvN5twe yEtQ== X-Gm-Message-State: AJcUukdYMx31ddvyfYi9X8nYhjQQavoZLgE9snlx1W5w+3O0pNWjpmW9 eiVzNDtG6tFJRn1+gqtynJZ8Y+tfTb1jwoZyruM= X-Received: by 2002:a9d:491e:: with SMTP id e30mr4931145otf.131.1545498442989; Sat, 22 Dec 2018 09:07:22 -0800 (PST) MIME-Version: 1.0 References: <1545392724-6637-1-git-send-email-jianxin.pan@amlogic.com> <1545392724-6637-3-git-send-email-jianxin.pan@amlogic.com> In-Reply-To: <1545392724-6637-3-git-send-email-jianxin.pan@amlogic.com> From: Martin Blumenstingl Date: Sat, 22 Dec 2018 18:07:12 +0100 Message-ID: Subject: Re: [PATCH RESEND v8 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller To: Jianxin Pan Cc: Boris Brezillon , linux-mtd@lists.infradead.org, Liang Yang , Yixun Lan , David Woodhouse , Miquel Raynal , Brian Norris , Marek Vasut , Richard Weinberger , Jerome Brunet , Neil Armstrong , Carlo Caione , Kevin Hilman , Rob Herring , Jian Hu , Hanjie Lin , Victor Wan , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jianxin, Hi Liang, On Fri, Dec 21, 2018 at 12:45 PM Jianxin Pan wrote: > > From: Liang Yang > > Add initial support for the Amlogic NAND flash controller which found > in the Meson-GXBB/GXL/AXG SoCs. > > Signed-off-by: Liang Yang > Signed-off-by: Yixun Lan > Signed-off-by: Jianxin Pan > --- > drivers/mtd/nand/raw/Kconfig | 10 + > drivers/mtd/nand/raw/Makefile | 1 + > drivers/mtd/nand/raw/meson_nand.c | 1468 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 1479 insertions(+) > create mode 100644 drivers/mtd/nand/raw/meson_nand.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index 1a55d3e..d05ff20 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA > is supported. Extra OOB bytes when using HW ECC are currently > not supported. > > +config MTD_NAND_MESON > + tristate "Support for NAND controller on Amlogic's Meson SoCs" > + depends on ARCH_MESON || COMPILE_TEST > + depends on COMMON_CLK_AMLOGIC > + select COMMON_CLK_REGMAP_MESON I believe that "depends on COMMON_CLK_AMLOGIC" and "select COMMON_CLK_REGMAP_MESON" are not necessary: the driver should build fine without them because it's only interfacing with the common clock framework. the common clock framework is enabled by ARCH_MESON and for the COMPILE_TEST case the common clock framework provides stub implementations inside the headers. > + select MFD_SYSCON > + help > + Enables support for NAND controller on Amlogic's Meson SoCs. > + This controller is found on Meson GXBB, GXL, AXG SoCs. you are explicitly mentioning GXBB here but you don't add a "GXBB" compatible. I suggest to shorten this sentence ("This controller is found on Meson SoCs.") because this driver can also support the 32-bit Meson8/Meson8b/Meson8m2 SoCs with minor adjustments. Regards Martin