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Subject: [PATCH 04/11] drm/komeda: Add komeda_crtc_mode_valid/fixup
Thread-Topic: [PATCH 04/11] drm/komeda: Add komeda_crtc_mode_valid/fixup
Thread-Index: AQHUm2qtO4uAfkpXZkCldalRPnu4xg==
Date:   Mon, 24 Dec 2018 09:25:58 +0000
Message-ID: <20181224092435.2792-5-james.qian.wang@arm.com>
References: <20181224092435.2792-1-james.qian.wang@arm.com>
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komeda_crtc_mode_valid compares the input mode->clk with main engine clk
and AXI clk, and reject the mode if the required pixel clk can not be
satisfied by main engine clk and AXI-clk.

Signed-off-by: James (Qian) Wang <james.qian.wang@arm.com>
---
 .../gpu/drm/arm/display/komeda/komeda_crtc.c  | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu=
/drm/arm/display/komeda/komeda_crtc.c
index b4640971e47e..05bdff137e50 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
@@ -90,9 +90,61 @@ komeda_crtc_atomic_flush(struct drm_crtc *crtc,
 	komeda_crtc_do_flush(crtc, old);
 }
=20
+static enum drm_mode_status
+komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mod=
e *m)
+{
+	struct komeda_dev *mdev =3D crtc->dev->dev_private;
+	struct komeda_crtc *kcrtc =3D to_kcrtc(crtc);
+	struct komeda_pipeline *master =3D kcrtc->master;
+	long mode_clk, pxlclk;
+
+	if (m->flags & DRM_MODE_FLAG_INTERLACE)
+		return MODE_NO_INTERLACE;
+
+	/* main clock/AXI clk must be faster than pxlclk*/
+	mode_clk =3D m->clock * 1000;
+	pxlclk =3D clk_round_rate(master->pxlclk, mode_clk);
+	if (pxlclk !=3D mode_clk) {
+		DRM_DEBUG_ATOMIC("pxlclk doesn't support %ld Hz\n", mode_clk);
+
+		return MODE_NOCLOCK;
+	}
+
+	if (clk_round_rate(mdev->mclk, mode_clk) < pxlclk) {
+		DRM_DEBUG_ATOMIC("mclk can't satisfy the requirement of %s-clk: %ld.\n",
+				 m->name, pxlclk);
+
+		return MODE_CLOCK_HIGH;
+	}
+
+	if (clk_round_rate(master->aclk, mode_clk) < pxlclk) {
+		DRM_DEBUG_ATOMIC("aclk can't satisfy the requirement of %s-clk: %ld.\n",
+				 m->name, pxlclk);
+
+		return MODE_CLOCK_HIGH;
+	}
+
+	return MODE_OK;
+}
+
+static bool komeda_crtc_mode_fixup(struct drm_crtc *crtc,
+				   const struct drm_display_mode *m,
+				   struct drm_display_mode *adjusted_mode)
+{
+	struct komeda_crtc *kcrtc =3D to_kcrtc(crtc);
+	struct komeda_pipeline *master =3D kcrtc->master;
+	long mode_clk =3D m->clock * 1000;
+
+	adjusted_mode->clock =3D clk_round_rate(master->pxlclk, mode_clk) / 1000;
+
+	return true;
+}
+
 struct drm_crtc_helper_funcs komeda_crtc_helper_funcs =3D {
 	.atomic_check	=3D komeda_crtc_atomic_check,
 	.atomic_flush	=3D komeda_crtc_atomic_flush,
+	.mode_valid	=3D komeda_crtc_mode_valid,
+	.mode_fixup	=3D komeda_crtc_mode_fixup,
 };
=20
 static const struct drm_crtc_funcs komeda_crtc_funcs =3D {
--=20
2.17.1