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[209.132.180.67]) by mx.google.com with ESMTP id h3si10112795pll.116.2018.12.24.23.58.06; Mon, 24 Dec 2018 23:58:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725856AbeLYHyw (ORCPT + 99 others); Tue, 25 Dec 2018 02:54:52 -0500 Received: from mail-sz2.amlogic.com ([211.162.65.114]:22608 "EHLO mail-sz2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725827AbeLYHyw (ORCPT ); Tue, 25 Dec 2018 02:54:52 -0500 Received: from [10.28.18.115] (10.28.18.115) by mail-sz2.amlogic.com (10.28.11.6) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Tue, 25 Dec 2018 15:55:16 +0800 From: Liang Yang Subject: Re: [PATCH RESEND v8 2/2] mtd: rawnand: meson: add support for Amlogic NAND flash controller To: Martin Blumenstingl , Jianxin Pan CC: Boris Brezillon , , Yixun Lan , David Woodhouse , Miquel Raynal , Brian Norris , Marek Vasut , Richard Weinberger , Jerome Brunet , Neil Armstrong , Carlo Caione , Kevin Hilman , Rob Herring , Jian Hu , Hanjie Lin , Victor Wan , , , References: <1545392724-6637-1-git-send-email-jianxin.pan@amlogic.com> <1545392724-6637-3-git-send-email-jianxin.pan@amlogic.com> Message-ID: <081f7986-0f8e-bd42-bae2-17058c7da301@amlogic.com> Date: Tue, 25 Dec 2018 15:55:16 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:60.0) Gecko/20100101 Thunderbird/60.3.3 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.28.18.115] X-ClientProxiedBy: mail-sz2.amlogic.com (10.28.11.6) To mail-sz2.amlogic.com (10.28.11.6) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On 2018/12/23 1:07, Martin Blumenstingl wrote: > Hi Jianxin, Hi Liang, > > On Fri, Dec 21, 2018 at 12:45 PM Jianxin Pan wrote: >> >> From: Liang Yang >> >> Add initial support for the Amlogic NAND flash controller which found >> in the Meson-GXBB/GXL/AXG SoCs. >> >> Signed-off-by: Liang Yang >> Signed-off-by: Yixun Lan >> Signed-off-by: Jianxin Pan >> --- >> drivers/mtd/nand/raw/Kconfig | 10 + >> drivers/mtd/nand/raw/Makefile | 1 + >> drivers/mtd/nand/raw/meson_nand.c | 1468 +++++++++++++++++++++++++++++++++++++ >> 3 files changed, 1479 insertions(+) >> create mode 100644 drivers/mtd/nand/raw/meson_nand.c >> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig >> index 1a55d3e..d05ff20 100644 >> --- a/drivers/mtd/nand/raw/Kconfig >> +++ b/drivers/mtd/nand/raw/Kconfig >> @@ -541,4 +541,14 @@ config MTD_NAND_TEGRA >> is supported. Extra OOB bytes when using HW ECC are currently >> not supported. >> >> +config MTD_NAND_MESON >> + tristate "Support for NAND controller on Amlogic's Meson SoCs" >> + depends on ARCH_MESON || COMPILE_TEST >> + depends on COMMON_CLK_AMLOGIC >> + select COMMON_CLK_REGMAP_MESON > I believe that "depends on COMMON_CLK_AMLOGIC" and "select > COMMON_CLK_REGMAP_MESON" are not necessary: > the driver should build fine without them because it's only > interfacing with the common clock framework. > the common clock framework is enabled by ARCH_MESON and for the > COMPILE_TEST case the common clock framework provides stub > implementations inside the headers. > >> + select MFD_SYSCON >> + help >> + Enables support for NAND controller on Amlogic's Meson SoCs. >> + This controller is found on Meson GXBB, GXL, AXG SoCs. > you are explicitly mentioning GXBB here but you don't add a "GXBB" compatible. > I suggest to shorten this sentence ("This controller is found on Meson > SoCs.") because this driver can also support the 32-bit > Meson8/Meson8b/Meson8m2 SoCs with minor adjustments. > we only have tested on Meson GXL and AXG platform, but it should support GXBB and Meson8/Meson8b/Meson8m2 and the differences between these controllers are only the base address of register and some SD_EMMC_CLOCK control bits. i think "This controller is found on Meson SoCs." is ok. > Regards > Martin > > . >