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[209.132.180.67]) by mx.google.com with ESMTP id r39si36508427pld.434.2018.12.27.09.16.18; Thu, 27 Dec 2018 09:16:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b="a/kGpxmC"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728868AbeL0D6R (ORCPT + 99 others); Wed, 26 Dec 2018 22:58:17 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:36608 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728511AbeL0D6Q (ORCPT ); Wed, 26 Dec 2018 22:58:16 -0500 Received: by mail-wm1-f65.google.com with SMTP id p6so16444502wmc.1 for ; Wed, 26 Dec 2018 19:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hWe2wpBd2D39MiGxDvt7Xxqdm6Vxh4rMpytdLJQK45o=; b=a/kGpxmCkjbt6lEu7r9USgPbiaqpYQvkfs8f1joj3Yg9ZkiHI7S2nOO02hzLrl3+u3 JvUFhpj6b+4NXnNB6C0zRDsBA+uEV1a9/gg7j56nPMJ8Q7WE5Hmc8wURgLaj3byd2yGq YX1zFb4Q732/LBnT8CntKygKBTFmvj+dHtjit8Jmkqubcd+Ct5MnRTrId+jJNNxN8k6s dPnOA24DNDjAcxiTq05HeVWTry2C0IDt2T2+0IYSiYAnmlt3vhf5Z91nEfumiRb/EPwB su8cc2iipgr+y3FKcYE1sNI/NgepZ1n1z/+cLEva7D5j0UohqbG6f2/qigIdMQ0mGVwr A/pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hWe2wpBd2D39MiGxDvt7Xxqdm6Vxh4rMpytdLJQK45o=; b=bxSq3XtGL1jpnLdXJ3753Mos4H3/gbIB0wY/mgrqvjPOAPJyfpQ1d7i8nI77/bPkFr kDpCh98qUfl9Xn3fJEYzBfM4TDDKcN71Z852h+NguWbaEPNliAjjqKZVfN4o2t1OvzMg N/MOJYySPYzYFciCXStUq9ugY+EAMzEFH26kEViTkkfCEYe7ZHV7rjHdaHdoc/FJvnIp I3piEMABmRPNqWtDSp/DW5FqAAPF1/x3RpR60r8n56g2UlYmKQNyX/xYL+rp4fee6THn hoM3KIf9xgBWYWo4AK5T9zIGG9RmgvCN3aQW7Gr5+MvKAL/laKzJtGg6uTMzLgqL00H3 mhjg== X-Gm-Message-State: AA+aEWY5UfBdld2zcmm7hBjYdja2ZgZ2WsESyIscJrrdlNGjA+FYIMmc ztia9oh15FC7KhNTS0yAV3shVKYzaaeL9681a3lhkA== X-Received: by 2002:a1c:a3c3:: with SMTP id m186mr19912199wme.16.1545883094136; Wed, 26 Dec 2018 19:58:14 -0800 (PST) MIME-Version: 1.0 References: <1545865741-22795-1-git-send-email-atish.patra@wdc.com> <1545865741-22795-4-git-send-email-atish.patra@wdc.com> In-Reply-To: <1545865741-22795-4-git-send-email-atish.patra@wdc.com> From: Anup Patel Date: Thu, 27 Dec 2018 09:28:03 +0530 Message-ID: Subject: Re: [PATCH 3/3] RISC-V: Fix non-smp kernel boot on SMP systems To: Atish Patra Cc: linux-riscv@lists.infradead.org, Albert Ou , Daniel Lezcano , Dmitriy Cherkasov , Jason Cooper , "linux-kernel@vger.kernel.org List" , Marc Zyngier , Michael Clark , Palmer Dabbelt , =?UTF-8?Q?Patrick_St=C3=A4hlin?= , Rob Herring , Thomas Gleixner , Damien Le Moal Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 27, 2018 at 4:39 AM Atish Patra wrote: > > In non-smp configuration, hartid can be higher that NR_CPUS. > riscv_of_processor_hartid should not be compared to hartid to > NR_CPUS in that case. Moreover, this function checks all the > DT properties of a hart node. NR_CPUS comparison seems out of > place. This only explains change in arch/riscv/kernel/cpu.c Create separate patch for it. > > Do cpuid comparison with NR_CPUs in smp setup code. Update the Create separate patch for change in arch/riscv/kernel/smp.c > drivers to handle appropriate code as well. Create separate patches for riscv_timer and irq-sifive-plic.c because they will probably go via different gitrepos. > > Signed-off-by: Atish Patra > --- > arch/riscv/kernel/cpu.c | 4 ---- > arch/riscv/kernel/smp.c | 1 - > arch/riscv/kernel/smpboot.c | 5 +++++ > drivers/clocksource/riscv_timer.c | 21 ++++++++++++++++++--- > drivers/irqchip/irq-sifive-plic.c | 5 +++++ > 5 files changed, 28 insertions(+), 8 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index b4a7d442..251ffab6 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -34,10 +34,6 @@ int riscv_of_processor_hartid(struct device_node *node) > pr_warn("Found CPU without hart ID\n"); > return -(ENODEV); > } > - if (hart >= NR_CPUS) { > - pr_info("Found hart ID %d, which is above NR_CPUs. Disabling this hart\n", hart); > - return -(ENODEV); > - } > > if (of_property_read_string(node, "status", &status)) { > pr_warn("CPU with hartid=%d has no \"status\" property\n", hart); > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > index 57b1383e..9ea7ac7d 100644 > --- a/arch/riscv/kernel/smp.c > +++ b/arch/riscv/kernel/smp.c > @@ -49,7 +49,6 @@ int riscv_hartid_to_cpuid(int hartid) > return i; > > pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); > - BUG(); Have a separate patch with explanation about why we don't need BUG() here. > return i; > } > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c > index bb8cd242..05291840 100644 > --- a/arch/riscv/kernel/smpboot.c > +++ b/arch/riscv/kernel/smpboot.c > @@ -66,6 +66,11 @@ void __init setup_smp(void) > found_boot_cpu = 1; > continue; > } > + if (cpuid >= NR_CPUS) { > + pr_warn("Invalid cpuid [%d] for hartid [%d]\n", > + cpuid, hart); > + break; > + } > > cpuid_to_hartid_map(cpuid) = hart; > set_cpu_possible(cpuid, true); > diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c > index 084e97dc..acf2af10 100644 > --- a/drivers/clocksource/riscv_timer.c > +++ b/drivers/clocksource/riscv_timer.c > @@ -89,20 +89,35 @@ static int __init riscv_timer_init_dt(struct device_node *n) > struct clocksource *cs; > > hartid = riscv_of_processor_hartid(n); > + if (hartid < 0) { > + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", > + n, hartid); > + return hartid; > + } > cpuid = riscv_hartid_to_cpuid(hartid); > > + if (cpuid < 0) > + pr_warn("Invalid cpuid for hartid [%d]\n", hartid); > + > if (cpuid != smp_processor_id()) > return 0; > > + pr_err("%s: Registering clocksource cpuid [%d] hartid [%d]\n", > + __func__, cpuid, hartid); > cs = per_cpu_ptr(&riscv_clocksource, cpuid); > - clocksource_register_hz(cs, riscv_timebase); > + error = clocksource_register_hz(cs, riscv_timebase); > > + if (error) { > + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > + error, cpuid); > + return error; > + } > error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, > "clockevents/riscv/timer:starting", > riscv_timer_starting_cpu, riscv_timer_dying_cpu); > if (error) > - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", > + error); > return error; > } > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index 357e9daf..254ecd76 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -237,6 +237,11 @@ static int __init plic_init(struct device_node *node, > } > > cpu = riscv_hartid_to_cpuid(hartid); > + if (cpu < 0) { > + pr_warn("Invalid cpuid for context %d\n", i); > + continue; > + } > + > handler = per_cpu_ptr(&plic_handlers, cpu); > handler->present = true; > handler->ctxid = i; > -- > 2.7.4 > Regards, Anup