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[209.132.180.67]) by mx.google.com with ESMTP id w16si35169670pga.328.2018.12.27.10.16.15; Thu, 27 Dec 2018 10:16:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rPMGkzPG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729629AbeL0GJ1 (ORCPT + 99 others); Thu, 27 Dec 2018 01:09:27 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40410 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728837AbeL0GJ0 (ORCPT ); Thu, 27 Dec 2018 01:09:26 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBR68n3g041829; Thu, 27 Dec 2018 00:08:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545890929; bh=iRuUmYWNVYIuUkKMwyMZMj3lnIZfqK26BHn7L/Vwj0M=; h=From:To:CC:Subject:Date; b=rPMGkzPGvmMN2ynAcjtPrs3l8nWcxURprbPQq3uOQhElf7FE+BlvuNNDElzg4XFds Ar3GeuHbn6P2F1qQ0ovLPM3DetjE9Jx6Sy5CGUDhNuO1+UhIFIy88k0giqwPjwy7fz rGxLjeEKZk/ENXBcRp0BUCJ4iBW97c1HevzBOT3Y= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBR68nbB103404 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Dec 2018 00:08:49 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Thu, 27 Dec 2018 00:08:49 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Thu, 27 Dec 2018 00:08:49 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBR68jsA020948; Thu, 27 Dec 2018 00:08:46 -0600 From: Lokesh Vutla To: , Nishanth Menon , Santosh Shilimkar , Rob Herring , , CC: Linux ARM Mailing List , , Tero Kristo , Sekhar Nori , Device Tree Mailing List , Peter Ujfalusi , Lokesh Vutla Subject: [PATCH v4 00/13] Add support for TISCI irqchip drivers Date: Thu, 27 Dec 2018 11:38:16 +0530 Message-ID: <20181227060829.5080-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI AM65x SoC based on K3 architecture, introduced support for Events which are message based interrupts with minimal latency. These events are not compatible with regular interrupts and are valid only through an event transport lane. An Interrupt Aggregator(INTA) is introduced to convert these events to interrupts. INTA can also group 64 events into a single interrupt. Now the SoC has many peripherals and a large number of event sources (time sync or DMA), the use of events is completely dependent on a user's specific application, which drives a need for maximum flexibility in which event sources are used in the system. It is also completely up to software control as to how the events are serviced. Because of the huge flexibility there are certain standard peripherals (like GPIO etc)where all interrupts cannot be directly corrected to host interrupt controller. For this purpose, Interrupt Router(INTR) is introduced in the SoC. INTR just does a classic interrupt redirection. So the SoC has 3 types of interrupt controllers: - GIC500 - Interrupt Router - Interrupt Aggregator Below is a diagrammatic view of how SoC integration of these interrupt controllers:(https://pastebin.ubuntu.com/p/9ngV3jdGj2/) Device Index-x Device Index-y | | | | .... \ / \ / \ (global events) / +---------------------------+ +---------+ | | | | | INTA | | GPIO | | | | | +---------------------------+ +---------+ | (vint) | | | \|/ | +---------------------------+ | | |<-------+ | INTR | | | +---------------------------+ | | \|/ (gic irq) +---------------------------+ | | | GIC | | | +---------------------------+ While at it, TISCI abstracts the handling of all above IRQ routes where interrupt sources are not directly connected to host interrupt controller. That would be configuration of Interrupt Aggregator and Interrupt Router. This series adds support for: - TISCI commands needed for IRQ configuration - Interrupt Router(INTR) and Interrupt Aggregator(INTA) drivers Changes since v3: - Fix documentation for Interrupt Router driver - Rebased on top of latest next. - Fully tested with DMA(using out of tree patches) - Fixed a build error with allmodconfig Grygorii Strashko (1): firmware: ti_sci: Add support to get TISCI handle using of_phandle Lokesh Vutla (11): firmware: ti_sci: Add support for RM core ops firmware: ti_sci: Add support for IRQ management firmware: ti_sci: Add helper apis to manage resources dt-bindings: irqchip: Introduce TISCI Interrupt router bindings irqchip: ti-sci-intr: Add support for Interrupt Router driver genirq/msi: Add support for allocating single MSI for a device genirq/msi: Add support for .msi_unprepare callback soc: ti: Add MSI domain support for K3 Interrupt Aggregator dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver soc: ti: am6: Enable interrupt controller drivers Peter Ujfalusi (1): firmware: ti_sci: Add RM mapping table for am654 .../bindings/arm/keystone/ti,sci.txt | 3 +- .../interrupt-controller/ti,sci-inta.txt | 74 ++ .../interrupt-controller/ti,sci-intr.txt | 85 ++ MAINTAINERS | 4 + drivers/firmware/ti_sci.c | 848 ++++++++++++++++++ drivers/firmware/ti_sci.h | 102 +++ drivers/irqchip/Kconfig | 23 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-ti-sci-inta.c | 561 ++++++++++++ drivers/irqchip/irq-ti-sci-intr.c | 310 +++++++ drivers/soc/ti/Kconfig | 11 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/k3_inta_msi.c | 193 ++++ include/linux/irqdomain.h | 1 + include/linux/msi.h | 12 + include/linux/soc/ti/k3_inta_msi.h | 22 + include/linux/soc/ti/ti_sci_protocol.h | 169 ++++ kernel/irq/msi.c | 72 +- 18 files changed, 2470 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt create mode 100644 drivers/irqchip/irq-ti-sci-inta.c create mode 100644 drivers/irqchip/irq-ti-sci-intr.c create mode 100644 drivers/soc/ti/k3_inta_msi.c create mode 100644 include/linux/soc/ti/k3_inta_msi.h -- 2.19.2