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[209.132.180.67]) by mx.google.com with ESMTP id a11si37275187pla.20.2018.12.27.10.16.54; Thu, 27 Dec 2018 10:17:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729412AbeL0He4 (ORCPT + 99 others); Thu, 27 Dec 2018 02:34:56 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:17512 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727950AbeL0Hez (ORCPT ); Thu, 27 Dec 2018 02:34:55 -0500 X-UUID: b650fc18a28d48beb3a896ae640f8ca3-20181227 X-UUID: b650fc18a28d48beb3a896ae640f8ca3-20181227 Received: from mtkcas34.mediatek.inc [(172.27.4.250)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1110584122; Thu, 27 Dec 2018 15:34:48 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Dec 2018 15:34:47 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Dec 2018 15:34:46 +0800 From: To: Bin Liu , Rob Herring CC: Greg Kroah-Hartman , Mark Rutland , Matthias Brugger , Alan Stern , , , , , , , Min Guo Subject: [PATCH 2/4] arm: dts: mt2701: Add usb2 device nodes Date: Thu, 27 Dec 2018 15:34:24 +0800 Message-ID: <1545896066-897-3-git-send-email-min.guo@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1545896066-897-1-git-send-email-min.guo@mediatek.com> References: <1545896066-897-1-git-send-email-min.guo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Min Guo Add musb nodes and usb2 phy nodes for MT2701 Signed-off-by: Min Guo --- arch/arm/boot/dts/mt2701-evb.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index be0edb3..2635911 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "mt2701.dtsi" / { @@ -60,6 +61,20 @@ >; default-brightness-level = <9>; }; + + extcon_usb: extcon_iddig { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 44 GPIO_ACTIVE_HIGH>; + }; + + usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &auxadc { @@ -229,3 +244,9 @@ &uart0 { status = "okay"; }; + +&usb2 { + vbus-supply = <&usb_vbus>; + extcon = <&extcon_usb>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 180377e..495ece9 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -670,6 +670,40 @@ }; }; + usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + phy-names = "usb2-phy"; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy0: usb-phy@11210000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@1a1c4800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; -- 1.9.1