Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp7273427imu; Thu, 27 Dec 2018 16:27:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN5Fc+bCpBLKt+6WqxlUW3XUtF4xxNyPQVCww2Nz9iamtGg+FCFa2HilEyHQ8H+eEFDU8AlJ X-Received: by 2002:a63:7e5b:: with SMTP id o27mr24299683pgn.214.1545956866528; Thu, 27 Dec 2018 16:27:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545956866; cv=none; d=google.com; s=arc-20160816; b=gUVNQB23tYxhTK2KtNO1ugwD8dUfgAdTJgYQ8/iqtMnyUViy2FmLUuOWOwO9JxLdEe pnhhrUlYfeKvs/+sfLBgYysIp3FiPo8Bn9NqrVMZNxOo5w22NiS6hesLickAJqr15F0/ DHjTf0UZ/DhFTDVXIJCT71CkuuXXH2XjYv1vI/Cua9MM/Wup8SIRJWjXzVpbXdUb3I0x dY1boQjw0Q/8YAP+8qAR6RmJDXHn70+M9B9Vflm83Xm1Fj6hHuaF8qAQNYXE3GAHTnNw KUc9wEkHHdvT2sHZGVvjIBq+1GDrqLTmRhJSp3JSHPUoaFsdoGVxy8d2kQVwhbCy+lfn bJjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=SScNoCyVoJoqfINOfbfqgdL8wWk/13Q1T2r909mMPx4=; b=p6gX10FC8ZT4D1O3xLs8ggWkZTNxSSbSEpqSSi+TO/spHtr1sUcapwy9lMBeLbiUgq h21Amqhc6LBTBrjoSKkCJ5Vq9c4FmCPy9l7POJyy1CblcKJJQe+Il/gAfKbJbN8u3eAB EI94n6CIPphxjs//CfXya1hDBmANkmoAvYlBszThDkX2hzIjoiBBZA8xLjBZ2/fjjEaz gn5V3hSm1MKhG4H5Ks2l6xpx72zjLY1nGTbTQYH5K1vcAF5uHb6dszPpxxO7RBe1DuJP eeCU5KN1f5ERuY3k5jq4efv54GZostUPmUXEhBdskc9Sy7LkZ0n6aqRW4P6CZylRWgtX KNGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i1si36708354pfj.276.2018.12.27.16.27.27; Thu, 27 Dec 2018 16:27:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730994AbeL0NLe (ORCPT + 99 others); Thu, 27 Dec 2018 08:11:34 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:3680 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726761AbeL0NLd (ORCPT ); Thu, 27 Dec 2018 08:11:33 -0500 X-UUID: b69ba60ec1fd4f30a6cb9e773edd9e70-20181227 X-UUID: b69ba60ec1fd4f30a6cb9e773edd9e70-20181227 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1015387575; Thu, 27 Dec 2018 21:11:04 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 27 Dec 2018 21:11:03 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 27 Dec 2018 21:11:03 +0800 From: To: Sean Wang , Vinod Koul , Rob Herring , Matthias Brugger , Dan Williams CC: , , , , , Subject: [PATCH v4] add support for Mediatek Command-Queue DMA controller on MT6765 SoC Date: Thu, 27 Dec 2018 21:10:56 +0800 Message-ID: <1545916258-18218-1-git-send-email-shun-chih.yu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v3: - simplify the ISR and management on descriptors by removing tasklet and ASYNC_TX_ENABLE_CHANNEL_SWITCH - remove useless field in mtk_cqdma_vdesc structure - change dev_info to dev_dbg - fix typos Changes since v2: - fix build warning for kernel with DMA address in 32-bit Changes since v1: - remove unused macros, typos - leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list Shun-Chih Yu (2): dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC .../devicetree/bindings/dma/mtk-cqdma.txt | 31 + drivers/dma/mediatek/Kconfig | 12 + drivers/dma/mediatek/Makefile | 1 + drivers/dma/mediatek/mtk-cqdma.c | 867 ++++++++++++++++++ 4 files changed, 911 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt create mode 100644 drivers/dma/mediatek/mtk-cqdma.c