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[209.132.180.67]) by mx.google.com with ESMTP id gn22si24286658plb.19.2018.12.28.21.39.45; Fri, 28 Dec 2018 21:40:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727870AbeL2AHR (ORCPT + 99 others); Fri, 28 Dec 2018 19:07:17 -0500 Received: from mail-it1-f195.google.com ([209.85.166.195]:36021 "EHLO mail-it1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726193AbeL2AHQ (ORCPT ); Fri, 28 Dec 2018 19:07:16 -0500 Received: by mail-it1-f195.google.com with SMTP id c9so28696403itj.1; Fri, 28 Dec 2018 16:07:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=yfMVC7zQ7bEaOMQTkSqqrnNV9XOHHvpwkP287tEPagk=; b=SnkMjsKiK1JaZLZC0yC18z7nTYEdf1o1J6PW8g9aTfSeE238vvQU+zwqkKx49GH2LW Uj0oGhkEWwhIUt7hKjikkxqeuZtDQ0HXOT/fuC1GJdXINS0VJTcaXVzkMG4A7EMzfl+q VdGPNrg8HgitbIhgXZvF7qOiKaRSBdZ3CbmypcS190Lb6OEbRSbl+vpwMNOprwTGudvv 0IjYFKxp+AOomNS8K+FvYWeqpG+LwQCxaW4iZUd+woC9zPUB1GIUwlGdcqtRw/aT4rmc HQystmqdxK9edlUHn0KDbLq5AA+9pcphUrskFPtGLyFkW3vMV5Ff94ivbBCMMgwJx/n0 498g== X-Gm-Message-State: AJcUukfHvN2JWSE89gwWjOm0lUiEY8SxmWv9MjpZ4VnN4dw+zUd9uzY/ 8bxFOtNDEU8DdseCN/JQvA== X-Received: by 2002:a24:214a:: with SMTP id e71mr16903940ita.60.1546042035478; Fri, 28 Dec 2018 16:07:15 -0800 (PST) Received: from localhost ([24.51.61.172]) by smtp.gmail.com with ESMTPSA id a12sm14732766ita.17.2018.12.28.16.07.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Dec 2018 16:07:14 -0800 (PST) Date: Fri, 28 Dec 2018 18:07:14 -0600 From: Rob Herring To: Lina Iyer Cc: sboyd@kernel.org, evgreen@chromium.org, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, thierry.reding@gmail.com, bjorn.andersson@linaro.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/7] dt-bindings: sdm845-pinctrl: add wakeup interrupt parent for GPIO Message-ID: <20181229000714.GA3654@bogus> References: <20181219221105.3004-1-ilina@codeaurora.org> <20181219221105.3004-5-ilina@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181219221105.3004-5-ilina@codeaurora.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 19, 2018 at 03:11:02PM -0700, Lina Iyer wrote: > SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO > routed to the PDC as interrupts that can be used to wake the system up > from deep low power modes and suspend. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Lina Iyer > --- > .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > index 665aadb5ea28..a522ca46667d 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > @@ -29,6 +29,11 @@ SDM845 platform. > Definition: must be 2. Specifying the pin number and flags, as defined > in > > +- wakeup-parent: > + Usage: optional > + Value type: > + Definition: A phandle to the wakeup interrupt controller for the SoC. Is this really necessary? Is there more than one possible wakeup-parent node? > + > - gpio-controller: > Usage: required > Value type: > @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the > mux function to select on those pin(s)/group(s), and various pin configuration > parameters, such as pull-up, drive strength, etc. > > - > PIN CONFIGURATION NODES: > > The name of each subnode is not important; all subnodes should be enumerated > @@ -160,6 +164,7 @@ Example: > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + wakeup-parent = <&pdc>; > > qup9_active: qup9-active { > mux { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >