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[209.132.180.67]) by mx.google.com with ESMTP id o11si37480953pll.160.2018.12.29.01.20.23; Sat, 29 Dec 2018 01:20:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726780AbeL1WEI (ORCPT + 99 others); Fri, 28 Dec 2018 17:04:08 -0500 Received: from mail-it1-f196.google.com ([209.85.166.196]:50190 "EHLO mail-it1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726066AbeL1WEI (ORCPT ); Fri, 28 Dec 2018 17:04:08 -0500 Received: by mail-it1-f196.google.com with SMTP id z7so30053414iti.0; Fri, 28 Dec 2018 14:04:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=notmpdDYWSi2JCcn64Q/8o1c94650SqabPpHm6d37c8=; b=OVNb/EXOqvZHCcMkzJsJYaimYbQGg/QFzRZPtyUtgn8EhN9ZYxk9tngzFxh9WxzXyO Sy1sMKYYHE0C8JjQTABgw9y94rs5/4opjMFO6IHRiNHj9WcYqoaAQ9R1qUSefuw3sdn/ oazyGJGpKhMC5anEwdk2vHPuzw16NZjYPL7bSnN1l7WeRRHgZliRrvdAWrKh1z/dfaEu CySGWtsZ8gsZ0LKu2/XC6ijrc6dF1wljydOSjrnHwsJ5xioH+ygiTrJe0z766TeQnCdn VHCDNeRGJoqTU5M22MD7SMYWrx8p4oByfh/ODkjxFt4G1hnBTT7x4x9pUbOrfe4XXaKn 5r8w== X-Gm-Message-State: AA+aEWZ8p5qZ8x9Ip7rOB8FJLUyY6MTsRX1ON/HVfUXIsfpRwCkKG3vQ b7H+QnEdCQo9kwdjyLfiMA== X-Received: by 2002:a24:ed4f:: with SMTP id r76mr17599014ith.17.1546034646772; Fri, 28 Dec 2018 14:04:06 -0800 (PST) Received: from localhost ([24.51.61.172]) by smtp.gmail.com with ESMTPSA id b188sm16853950itc.9.2018.12.28.14.04.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Dec 2018 14:04:06 -0800 (PST) Date: Fri, 28 Dec 2018 16:04:05 -0600 From: Rob Herring To: Erin Lo Cc: Matthias Brugger , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd , devicetree@vger.kernel.org, srv_heupstream , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, yingjoe.chen@mediatek.com, mars.cheng@mediatek.com, eddie.huang@mediatek.com, linux-clk@vger.kernel.org, Zhiyong Tao Subject: Re: [PATCH v5 5/6] dt-bindings: pinctrl: mt8183: add binding document Message-ID: <20181228220405.GA8739@bogus> References: <1545984581-25843-1-git-send-email-erin.lo@mediatek.com> <1545984581-25843-6-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1545984581-25843-6-git-send-email-erin.lo@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 28, 2018 at 04:09:40PM +0800, Erin Lo wrote: > From: Zhiyong Tao > > The commit adds mt8183 compatible node in binding document. > > Signed-off-by: Zhiyong Tao > Signed-off-by: Erin Lo > --- > .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 110 +++++++++++++++++++++ > 1 file changed, 110 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > new file mode 100644 > index 0000000..7b5285e > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > @@ -0,0 +1,110 @@ > +* Mediatek MT8183 Pin Controller > + > +The Mediatek's Pin controller is used to control SoC pins. > + > +Required properties: > +- compatible: value should be one of the following. > + "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl. > +- gpio-controller : Marks the device node as a gpio controller. > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO > + binding is used, the amount of cells must be specified as 2. See the below > + mentioned gpio binding representation for description of particular cells. > +- gpio-ranges : gpio valid number range. > + > + Eg: <&pio 6 0> > + <[phandle of the gpio controller node] > + [line number within the gpio controller] > + [flags]> > + > + Values for gpio specifier: > + - Line number: is a value between 0 to 202. > + - Flags: bit field of flags, as defined in . > + Only the following flags are supported: > + 0 - GPIO_ACTIVE_HIGH > + 1 - GPIO_ACTIVE_LOW > + > +Optional properties: > +- reg: physicall address base for gpio base registers. s/physicall/physical/ reg should never be optional. Need to say how many reg entries. > +- reg-names: gpio base registers name. Need to say what are the names. However, I don't find the names in the example all that useful, so I'd just drop it. > +- interrupt-controller: Marks the device node as an interrupt controller > +- #interrupt-cells: Should be two. > +- interrupts : The interrupt outputs from the controller. > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices. > + > +Subnode format > +A pinctrl node should contain at least one subnodes representing the > +pinctrl groups available on the machine. Each subnode will list the > +pins it needs, and how they should be configured, with regard to muxer > +configuration, pullups, drive strength, input enable/disable and input schmitt. > + > + node { > + pinmux = ; > + GENERIC_PINCONFIG; > + }; > + > +Required properties: > +- pinmux: integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are defined > + as macros in boot/dts/-pinfunc.h directly. > + > +Optional properties: > +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, > + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, > + input-schmitt-enable, input-schmitt-disable and drive-strength are valid. > + > + Some special pins have extra pull up strength, there are R0 and R1 pull-up > + resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. > + So when config mediatek,pull-up-adv or mediatek,pull-down-adv, > + it support arguments for those special pins. > + > + When config drive-strength, it can support some arguments, such as > + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. > + > +Examples: > + > +#include "mt8183-pinfunc.h" > + > +... > +{ > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11F20000 0 0x1000>, > + <0 0x11E80000 0 0x1000>, > + <0 0x11E70000 0 0x1000>, > + <0 0x11E90000 0 0x1000>, > + <0 0x11D30000 0 0x1000>, > + <0 0x11D20000 0 0x1000>, > + <0 0x11C50000 0 0x1000>, > + <0 0x11F30000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; > + #interrupt-cells = <2>; > + > + i2c0_pins_a: i2c0@0 { unit-address without reg property is not valid. > + pins1 { > + pinmux = , > + ; > + mediatek,pull-up-adv = <11>; > + }; > + }; > + > + i2c1_pins_a: i2c1@0 { > + pins { > + pinmux = , > + ; > + mediatek,pull-down-adv = <10>; > + }; > + }; > + ... > + }; > +}; > -- > 1.9.1 >