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a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=K1XQmbL2MFf3kQsLtSuP+3Ovn6DFXnAtZHCnBfr+qO8=; b=gblVY1D94ag+pW6Dh73ALFtyGVezV1SnyHyYbrmjTSEK8NIvv30WGA67eGV1YTJN8xlJMtkErdq4nU+YsybHZc6EAMyg5nPVLARghtAAP7L+CKODIbOLW1feGpX981KA0XGgJ7KATeibmM0ge4sjoeASvDYz6P+nPHi//rDglZU= Received: from AM3PR08MB0611.eurprd08.prod.outlook.com (10.163.188.149) by AM3PR08MB0658.eurprd08.prod.outlook.com (10.163.189.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1495.6; Thu, 3 Jan 2019 11:40:05 +0000 Received: from AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::3c73:534c:9c6e:352d]) by AM3PR08MB0611.eurprd08.prod.outlook.com ([fe80::3c73:534c:9c6e:352d%2]) with mapi id 15.20.1495.005; Thu, 3 Jan 2019 11:40:05 +0000 From: "james qian wang (Arm Technology China)" To: Liviu Dudau , "daniel.vetter@ffwll.ch" , "rdunlap@infradead.org" , "robh+dt@kernel.org" CC: "Jonathan Chai (Arm Technology China)" , Brian Starkey , "Julien Yin (Arm Technology China)" , "thomas Sun (Arm Technology China)" , Alexandru-Cosmin Gheorghe , "Lowry Li (Arm Technology China)" , Ayan Halder , "Tiannan Zhu (Arm Technology China)" , "Jin Gao (Arm Technology China)" , "Yiqi Kang (Arm Technology China)" , nd , "malidp@foss.arm.com" , "maarten.lankhorst@linux.intel.com" , "maxime.ripard@bootlin.com" , "sean@poorly.run" , "corbet@lwn.net" , "linux-doc@vger.kernel.org" , "mchehab+samsung@kernel.org" , "davem@davemloft.net" , "gregkh@linuxfoundation.org" , "akpm@linux-foundation.org" , "nicolas.ferre@microchip.com" , "arnd@arndb.de" , Mark Rutland , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "airlied@linux.ie" , "yamada.masahiro@socionext.com" , "james qian wang (Arm Technology China)" Subject: [PATCH v4 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Topic: [PATCH v4 2/9] dt/bindings: drm/komeda: Add DT bindings for ARM display processor D71 Thread-Index: AQHUo1kR3aloiKD41Uys9n4X8zOt2A== Date: Thu, 3 Jan 2019 11:40:04 +0000 Message-ID: <20190103113841.15403-3-james.qian.wang@arm.com> References: <20190103113841.15403-1-james.qian.wang@arm.com> In-Reply-To: <20190103113841.15403-1-james.qian.wang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: SY2PR01CA0046.ausprd01.prod.outlook.com (2603:10c6:1:15::34) To AM3PR08MB0611.eurprd08.prod.outlook.com (2a01:111:e400:c408::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=james.qian.wang@arm.com; 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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: RiqskkCV/P+In5R4lgzlnFvOz30LbLfyLkxGjzOWQYKSPVHevShbu3yi+K6RXl1ImSFb1ivKJqOJ+gP7K2FKjkpLYSF+5Z8CRXbnAptyCLa3QofnpOqu65bg+sD/HOk3dTrkhmO7WjPwYabv66nrai1v7zDbeJ4ASMeKU7mie/4pER6+g9w4xotqTm9igH/Hhf8MsdxCMVVYg+FwW0reyP+w37G3KV93tnM2MiYEdXcIqIopdx4RoLVvVPjb3xXKZjMyj2zdJ/eH4yfYUVv5KMI0byPRxBLw6UWG8N4Txqh1Hc7ZqIMsdjtwJ5Vs1Y1E spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 295b4777-ff29-4fbc-d8aa-08d671703431 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jan 2019 11:40:04.9595 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0658 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "james qian wang (Arm Technology China)" Add DT bindings documentation for the ARM display processor D71 and later IPs. Changes in v4: - Deleted unnecessary address-cells, size-cells [Liviu Dudau] Changes in v3: - Deleted unnecessary property: interrupt-names. - Dropped 'ports' and moving 'port' up a level. Signed-off-by: James Qian Wang (Arm Technology China) Reviewed-by: Liviu Dudau --- .../bindings/display/arm/arm,komeda.txt | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/arm/arm,komed= a.txt diff --git a/Documentation/devicetree/bindings/display/arm/arm,komeda.txt b= /Documentation/devicetree/bindings/display/arm/arm,komeda.txt new file mode 100644 index 000000000000..919d651d3e8c --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm/arm,komeda.txt @@ -0,0 +1,73 @@ +Device Tree bindings for Arm Komeda display driver + +Required properties: +- compatible: Should be "arm,mali-d71" +- reg: Physical base address and length of the registers in the system +- interrupts: the interrupt line number of the device in the system +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: A list of clock names. It should contain: + - "mclk": for the main processor clock + - "pclk": for the APB interface clock +- #address-cells: Must be 1 +- #size-cells: Must be 0 + +Required properties for sub-node: pipeline@nq +Each device contains one or two pipeline sub-nodes (at least one), each +pipeline node should provide properties: +- reg: Zero-indexed identifier for the pipeline +- clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' +- clock-names: should contain: + - "pxclk": pixel clock + - "aclk": AXI interface clock + +- port: each pipeline connect to an encoder input port. The connection is + modeled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt + +Optional properties: + - memory-region: phandle to a node describing memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) + to be used for the framebuffer; if not present, the framebuffer may + be located anywhere in memory. + +Example: +/ { + ... + + dp0: display@c00000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "arm,mali-d71"; + reg =3D <0xc00000 0x20000>; + interrupts =3D <0 168 4>; + clocks =3D <&dpu_mclk>, <&dpu_aclk>; + clock-names =3D "mclk", "pclk"; + + dp0_pipe0: pipeline@0 { + clocks =3D <&fpgaosc2>, <&dpu_aclk>; + clock-names =3D "pxclk", "aclk"; + reg =3D <0>; + + port@0 { + dp0_pipe0_out: endpoint { + remote-endpoint =3D <&db_dvi0_in>; + }; + }; + }; + + dp0_pipe1: pipeline@1 { + clocks =3D <&fpgaosc2>, <&dpu_aclk>; + clock-names =3D "pxclk", "aclk"; + reg =3D <1>; + + port@0 { + dp0_pipe1_out: endpoint { + remote-endpoint =3D <&db_dvi1_in>; + }; + }; + }; + }; + ... +}; --=20 2.17.1