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From:   "S, Shirish" <Shirish.S@amd.com>
CC:     "S, Shirish" <Shirish.S@amd.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
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        <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4"
 to more models
Thread-Topic: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank
 4" to more models
Thread-Index: AQHUpBEV9bvGRHbRhkWGjQZ6rd+J4w==
Date:   Fri, 4 Jan 2019 09:37:18 +0000
Message-ID: <1546594609-22403-2-git-send-email-shirish.s@amd.com>
References: <1546594609-22403-1-git-send-email-shirish.s@amd.com>
In-Reply-To: <1546594609-22403-1-git-send-email-shirish.s@amd.com>
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The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.

"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"

This patch extends the quirk to make it applicable till 7th Generation,
so as to address the below warning at boot:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S <shirish.s@amd.com>
---
 arch/x86/kernel/cpu/mce/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.=
c
index 672c722..051b536 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x=
86 *c)
 		 * they're not supported there.
 		 */
 		if (c->x86 =3D=3D 0x15 &&
-		    (c->x86_model >=3D 0x10 && c->x86_model <=3D 0x1f)) {
+		    (c->x86_model >=3D 0x10 && c->x86_model <=3D 0x7f)) {
 			int i;
 			u64 hwcr;
 			bool need_toggle;
--=20
2.7.4