Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp3378515imu; Mon, 7 Jan 2019 02:10:57 -0800 (PST) X-Google-Smtp-Source: ALg8bN7U/cBaB4707ESeoRiZpkttjij6E+fLBfvTs8Linohi7eD+XhQ3H71oDvCf1nOxY51kgLwU X-Received: by 2002:aa7:8758:: with SMTP id g24mr61321831pfo.250.1546855857286; Mon, 07 Jan 2019 02:10:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1546855857; cv=none; d=google.com; s=arc-20160816; b=CjL42JIg/Ap1rPfFdn01FHgqL/8gfDTh2OImPOyBZ/uql39g7/zIIu94N3mlszO/mj fuLb91vebw0ECTYb4iCzoc7+BcgM9FVCW5RCNIhCch9Br1QlrO33GUnVN8+Vjg3h6HmL IKMibqTOEs2CE6JcSd1qXm9h2x48x84eMJ5G+Q2f61ItqJjN+OJzGJtID6EtQFCzr+4i QRkLOzuef4C9ofW7iUo/8kifN2VS0a+5rYGNygYIVlRgsWGkzEMVxxcL0Gai0snTiWUo CosHIZytDmvPgmAnEJkUja4kzHdQwT43lXrMF+KowThYqMbqPkNYD0SXw9BxQHEQ8+1H teHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=TF9Rls4BwefNh/zH36iPeSZ12hqQpNBsAE7SF1IYbow=; b=osxSiMGtVwkPhdTgwcjTkWWdo49+9ba7mERwxmsMMUk3sCEnoJmlnXJjMbEAhOC/y9 AmVdu//Hv2o+3hGM7QUjcM9vkVOUqwZ4g5VoX8z6vEST+gdQJzPrTnhdP/9SDprk7KnA 24AmBS+kytY+UtYuZr+BVAFYGbbRlDbcO2y5mysO6BWdGGnQbfaapkMW1UvJG3+Umxcr RVMzNsoAppj4HQr8QNt6FkLqn9C3uFuzyuNUxml0Lw65f5SgggqAaj9KXjxiAANHhjEt CdjKpyZVqrLzZZLNPZD17mdYt7jRP6UrYzuFWVFDTR40iujIk6Zumiu/oTvMb+aM/H+/ dFGQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m11si5162110plt.26.2019.01.07.02.10.41; Mon, 07 Jan 2019 02:10:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726834AbfAGKI3 (ORCPT + 99 others); Mon, 7 Jan 2019 05:08:29 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:42940 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726714AbfAGKIT (ORCPT ); Mon, 7 Jan 2019 05:08:19 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x07A3hjY001107; Mon, 7 Jan 2019 11:07:58 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2ptvjffee0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 07 Jan 2019 11:07:58 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0A9E43A; Mon, 7 Jan 2019 10:07:56 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CA75D2A00; Mon, 7 Jan 2019 10:07:56 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 7 Jan 2019 11:07:56 +0100 From: Fabrice Gasnier To: , CC: , , , , , , , , , Subject: [RESEND PATCH v2 0/3] mfd: syscon: Add optional clock support needed on stm32 Date: Mon, 7 Jan 2019 11:07:42 +0100 Message-ID: <1546855665-26218-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-01-07_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 syscfg registers are accessed using syscon. It needs syscfg clock to be enabled while accessing registers. This adds support for optional clock on syscon, and the relevant clock in stm32mp157 device tree. Changes in v2: - move clocks to specific bindings using syscon as per Rob's comment Fabrice Gasnier (3): dt-bindings: stm32: syscon: add clock support mfd: syscon: Add optional clock support ARM: dts: stm32: Add clock on stm32mp157c syscfg .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 2 ++ arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/mfd/syscon.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) -- 1.9.1