Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp463491imu; Wed, 9 Jan 2019 00:25:15 -0800 (PST) X-Google-Smtp-Source: ALg8bN4r3IJhDKlvmC59L5ntUOoN7lD0WJRck1EY37jT1m8FibgByfBI9Nl3YU0t9EsqYhbufYIK X-Received: by 2002:a62:2c4d:: with SMTP id s74mr4991984pfs.6.1547022315145; Wed, 09 Jan 2019 00:25:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547022315; cv=none; d=google.com; s=arc-20160816; b=En6UQfNFR0tmP7xWd1+jOACTqzYhxTH7Cdj8s7u/BZ8cRB36gNjAfYEh+uzcKuvV4b ZeFGMPyb0qE5eUZXI5zRthDUqlOT8BkBlG9J2OygbMaW01FPVP/a5vW1isN/2gUwkgLe KxLzSudw9pVb0XJUITU18hKbtRy+akBBU7F2x2CQljlwoFUU7wRHZhpACI676MY6WfDu hKb1C9MiFwP4a+o1clsZLKqrl/PPZHaXe8NhkP45z/U2otR4j6kwQGQF2Mzo71TQJsM+ W4ecos15lTv9qcJyJXDqMIK7HQHXfRyxo3psa5V4iDAabFsZsXV0FOBYrcLjdRSfzau5 zf7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=jYJEO2rVbMF/Dh6FjBUOVgzxZa16Y18ccgFtS/42/mI=; b=BefbmtifYfz1+AXRQ1VpiI1L/0n7+5gTT1zG/aawfgm5XGCwK3s/YXhF40d22qwPB9 Fl4hbAD7+ZrfYafHwe3DsN9YMmuOC/qqT2Vk65+TdLR/wXyG0c0Jj1nDz+bV26QkJHpY d+NcBat6WNvcCcgxXPd/qd9+CWA4MlniXJIYvKvYrzM5/V7CjusNYzyEELn+XPhXspft cLB0qS5icmd9GLv6klTiI+gsWfqWSxvbOPtAMY/61qKlmBq2NETNupnV3To0B286bMSW Ff0zuMlNLl/qrkf2gWRw9Z0QDqstKk2J3mO6GVHvXQNteNiVUNG0ucl8P278WgtcKmcQ DEEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x61si3314539plb.303.2019.01.09.00.24.59; Wed, 09 Jan 2019 00:25:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729886AbfAIIWV (ORCPT + 99 others); Wed, 9 Jan 2019 03:22:21 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:5048 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729603AbfAIIWV (ORCPT ); Wed, 9 Jan 2019 03:22:21 -0500 X-UUID: bf50859f042c45df81a81458f989f227-20190109 X-UUID: bf50859f042c45df81a81458f989f227-20190109 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1077249081; Wed, 09 Jan 2019 16:22:02 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Jan 2019 16:22:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Jan 2019 16:22:01 +0800 From: Seiya Wang To: Rob Herring , Mark Rutland , Matthias Brugger CC: , , , , , Seiya Wang Subject: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173 Date: Wed, 9 Jan 2019 16:21:43 +0800 Message-ID: <20190109082143.26468-1-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the device nodes of ARM Performance Monitor Uint for mt8173. Signed-off-by: Seiya Wang --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 412ffd4d426b..44374c506a1c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -216,6 +216,20 @@ }; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; method = "smc"; -- 2.14.1