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[209.132.180.67]) by mx.google.com with ESMTP id j13si27710417pgi.227.2019.01.09.12.52.22; Wed, 09 Jan 2019 12:52:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=uK8Kbihk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727992AbfAIS7C (ORCPT + 99 others); Wed, 9 Jan 2019 13:59:02 -0500 Received: from mail.kernel.org ([198.145.29.99]:55328 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727878AbfAIS7C (ORCPT ); Wed, 9 Jan 2019 13:59:02 -0500 Received: from localhost (unknown [104.132.0.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AD69B20859; Wed, 9 Jan 2019 18:59:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1547060341; bh=zzSA5aRRwHqiJsUJtmpgsyL4dwgZua8xQR/+YxkdSNA=; h=Subject:Cc:To:In-Reply-To:From:References:Date:From; b=uK8KbihkiFQA21MuZE6OxG+cZm+JFeKNC11OCG4A5CXNcg7ZxPFVVUZTB8owJ1XdT q37tmTH4E18+YFiBAhW9NTt+yDFGbL1t7HgFI+Ee4iIRPyFQ2HpSoD0WMEJb1cxj+p XXKp16ANF6i1J417vqiZ6CQW9L+8K0VPCJd3xLXI= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v1 2/6] clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998 Cc: bjorn.andersson@linaro.org, andy.gross@linaro.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, balbi@kernel.org, linux-usb@vger.kernel.org, Jeffrey Hugo To: Jeffrey Hugo , mturquette@baylibre.com In-Reply-To: <1546620615-2389-1-git-send-email-jhugo@codeaurora.org> From: Stephen Boyd User-Agent: alot/0.8 References: <1546620615-2389-1-git-send-email-jhugo@codeaurora.org> Message-ID: <154706034090.15366.11081837995313995010@swboyd.mtv.corp.google.com> Date: Wed, 09 Jan 2019 10:59:00 -0800 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Jeffrey Hugo (2019-01-04 08:50:15) > The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by > the phy during init. The clock needs to be enabled during the init > sequence, but may not be fully active until after the init sequence is > complete. This causes a catch-22 if the clock status is checked during > enable. As a result, skip the checks to avoid the troubling situation. I will ask again, is anyone going to fix this in the phy driver? In theory it isn't needed if the phy driver can do things differently, but last time I checked I was told that the phy team said it had to be done this way.