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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id l20sm122848439wrb.93.2019.01.09.13.23.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jan 2019 13:23:02 -0800 (PST) Subject: Re: [PATCH v5 1/2] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller driver To: Sergei Shtylyov , Geert Uytterhoeven Cc: Mason Yang , Mark Brown , Linux Kernel Mailing List , linux-spi , Boris Brezillon , Linux-Renesas , Geert Uytterhoeven , juliensu@mxic.com.tw, Simon Horman , zhengxunli@mxic.com.tw References: <1546921020-20436-1-git-send-email-masonccyang@mxic.com.tw> <1546921020-20436-2-git-send-email-masonccyang@mxic.com.tw> <74a5fba6-a77e-f71b-ce49-405fee8e0fda@cogentembedded.com> From: Marek Vasut Openpgp: preference=signencrypt Message-ID: Date: Wed, 9 Jan 2019 22:23:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/9/19 8:04 PM, Sergei Shtylyov wrote: > On 01/09/2019 09:49 PM, Geert Uytterhoeven wrote: > >>>> Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller. >>>> >>>> Signed-off-by: Mason Yang >>> >>> You now need to add: >>> >>> Signed-off-by: Sergei Shtylyov >> >>>> --- a/drivers/spi/Kconfig >>>> +++ b/drivers/spi/Kconfig >>>> @@ -544,6 +544,12 @@ config SPI_RSPI >>>> help >>>> SPI driver for Renesas RSPI and QSPI blocks. >>>> >>>> +config SPI_RENESAS_RPC_IF >>> >>> Since the driver is called without -IF suffix, I wouldn't use it in the >>> Kconfig name either, the following is enough: >>> >>>> + tristate "Renesas R-Car Gen3 RPC-IF SPI controller" >>>> + depends on ARCH_RENESAS || COMPILE_TEST >>> >>> Judging on the compilation error reported by the 0-day bot about readq(), >>> we now need to depend on 64BIT or something... >> >> IIRC, this hardware block is also used on RZ/A, which is 32-bit. > > I'm not seeing it in the "RZ/A1H Group, RZ/A1M Group User’s Manual: Hardware" > Rev 3.00. What SoC did you have in mind? At least the GR Peach boots from this block, so that one :) -- Best regards, Marek Vasut