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[209.132.180.67]) by mx.google.com with ESMTP id h85si26132492pfd.27.2019.01.11.03.10.13; Fri, 11 Jan 2019 03:10:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BoHS+y2p; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730186AbfAKK2x (ORCPT + 99 others); Fri, 11 Jan 2019 05:28:53 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58638 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725807AbfAKK2x (ORCPT ); Fri, 11 Jan 2019 05:28:53 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0BASKJi075001; Fri, 11 Jan 2019 04:28:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547202500; bh=+zDvpcwvNs2Tzut97PtVsFJa5+nb/1iMKUfpE6GKYR8=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=BoHS+y2pKmjB2Aw+8dFH4CqAPJZxXGAPJOa8YSm9BbtIX7yIjjTMQB5lfFLGKvwhV 99vS5/75xQsoMGZpfO5PfcElpYPR/xMDUkWk9UITPGiLG0c2u7zpESrm8CsRF7iZ+s dtRtIX0coRZwlGtzWUuWxoGzO/vrgUVOgE1eybtg= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0BASKta120605 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Jan 2019 04:28:20 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 11 Jan 2019 04:28:19 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 11 Jan 2019 04:28:19 -0600 Received: from [172.24.190.117] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0BASFEE014716; Fri, 11 Jan 2019 04:28:16 -0600 Subject: Re: [PATCH v4 00/13] Add support for TISCI irqchip drivers To: , Nishanth Menon , Santosh Shilimkar , Rob Herring , , CC: Linux ARM Mailing List , , Tero Kristo , Sekhar Nori , Device Tree Mailing List , Peter Ujfalusi References: <20181227060829.5080-1-lokeshvutla@ti.com> From: Lokesh Vutla Message-ID: <620377f9-719f-0ce2-2b70-87fb6aa5d764@ti.com> Date: Fri, 11 Jan 2019 15:58:00 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181227060829.5080-1-lokeshvutla@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 27/12/18 11:38 AM, Lokesh Vutla wrote: > TI AM65x SoC based on K3 architecture, introduced support for Events > which are message based interrupts with minimal latency. These events > are not compatible with regular interrupts and are valid only through > an event transport lane. An Interrupt Aggregator(INTA) is introduced > to convert these events to interrupts. INTA can also group 64 events > into a single interrupt. Now the SoC has many peripherals and a large > number of event sources (time sync or DMA), the use of events is > completely dependent on a user's specific application, which drives a > need for maximum flexibility in which event sources are used in the > system. It is also completely up to software control as to how the > events are serviced. > > Because of the huge flexibility there are certain standard peripherals > (like GPIO etc)where all interrupts cannot be directly corrected to host > interrupt controller. For this purpose, Interrupt Router(INTR) is > introduced in the SoC. INTR just does a classic interrupt redirection. > > So the SoC has 3 types of interrupt controllers: > - GIC500 > - Interrupt Router > - Interrupt Aggregator > > Below is a diagrammatic view of how SoC integration of these interrupt > controllers:(https://pastebin.ubuntu.com/p/9ngV3jdGj2/) > > Device Index-x Device Index-y > | | > | | > .... > \ / > \ / > \ (global events) / > +---------------------------+ +---------+ > | | | | > | INTA | | GPIO | > | | | | > +---------------------------+ +---------+ > | (vint) | > | | > \|/ | > +---------------------------+ | > | |<-------+ > | INTR | > | | > +---------------------------+ > | > | > \|/ (gic irq) > +---------------------------+ > | | > | GIC | > | | > +---------------------------+ Can you please take a look at the MSI changes and provide your feedback? There are few places(mentioned in the respective patches) where I felt I am hacking around. It would be really helpful if you give any direction for such hacks. Thanks and regards, Lokesh