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[209.132.180.67]) by mx.google.com with ESMTP id s66si3645378pgs.115.2019.01.15.07.55.59; Tue, 15 Jan 2019 07:56:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pRtGyIda; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730106AbfAONzu (ORCPT + 99 others); Tue, 15 Jan 2019 08:55:50 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33552 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729099AbfAONzt (ORCPT ); Tue, 15 Jan 2019 08:55:49 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0FDtUgR096889; Tue, 15 Jan 2019 07:55:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547560530; bh=M4E9szcMy2s/1G1NcDsPyh7e/Ea7sPKwxtbQVHhwljQ=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=pRtGyIdaRglXIN7p6XoRFmsBFfVsG5AQvr0cYrZxdQusWrTu7n/iTsIszAOSsbo6r y+tH8HFY2sy/49gUoBffBaYNFVyyk3RC9hLpz175dHEzxDCN0ZGvqHPyC8BvcSk6VJ pUkOA+Q/SXsR+Ecnz0SuLSHf28dVmVAvvztcPiT0= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0FDtU8R119636 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Jan 2019 07:55:30 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 15 Jan 2019 07:55:29 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 15 Jan 2019 07:55:29 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0FDtTtW025526; Tue, 15 Jan 2019 07:55:29 -0600 Date: Tue, 15 Jan 2019 07:54:57 -0600 From: Nishanth Menon To: Lokesh Vutla CC: , Santosh Shilimkar , Rob Herring , , , Linux ARM Mailing List , , Tero Kristo , Sekhar Nori , Device Tree Mailing List , Peter Ujfalusi Subject: Re: [RFC PATCH v4 13/13] soc: ti: am6: Enable interrupt controller drivers Message-ID: <20190115135457.2x6huvgtth2yjhhq@kahuna> References: <20181227060829.5080-1-lokeshvutla@ti.com> <20181227061313.5451-1-lokeshvutla@ti.com> <20181227061313.5451-13-lokeshvutla@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20181227061313.5451-13-lokeshvutla@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11:43-20181227, Lokesh Vutla wrote: > Select all the TISCI dependent interrupt controller drivers > for AM6 SoC. > > Suggested-by: Marc Zyngier > Signed-off-by: Lokesh Vutla > --- > drivers/soc/ti/Kconfig | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig > index 7640490c2a6a..145b701a3d96 100644 > --- a/drivers/soc/ti/Kconfig > +++ b/drivers/soc/ti/Kconfig > @@ -5,6 +5,11 @@ if ARCH_K3 > > config ARCH_K3_AM6_SOC > bool "K3 AM6 SoC" > + select MAILBOX > + select TI_MESSAGE_MANAGER > + select TI_SCI_PROTOCOL > + select TI_SCI_INTR_IRQCHIP > + select TI_SCI_INTA_IRQCHIP Sorry for joining the party late.. but just 2 cents for thought.. Is'nt imply better than select here? for a very tiny kernel, it is possible to boot kernel up and TISCI and mailbox could be modules as well.. I know it is a theoretical concept, but it may be helpful (esp during pre-silicon time frame, at least during start, I usually start with almost everything other than the CPU cores and PSCI disabled). there is not much you can do with it ofcourse, but it helps me with a clean start. > help > Enable support for TI's AM6 SoC Family support > > -- > 2.19.2 > -- Regards, Nishanth Menon