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From:   Vineet Gupta <vineet.gupta1@synopsys.com>
To:     Eugeniy Paltsev <eugeniy.paltsev@synopsys.com>,
        "linux-snps-arc@lists.infradead.org" 
        <linux-snps-arc@lists.infradead.org>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Alexey Brodkin" <alexey.brodkin@synopsys.com>
Subject: Re: [PATCH 1/2] ARCv2: LIB: memeset: fix doing prefetchw outside of
 buffer
Thread-Topic: [PATCH 1/2] ARCv2: LIB: memeset: fix doing prefetchw outside
 of buffer
Thread-Index: AQHUrBw2ZJte6r90DkSex+vHyLGaMw==
Date:   Tue, 15 Jan 2019 16:58:17 +0000
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References: <20190114151649.32726-1-Eugeniy.Paltsev@synopsys.com>
 <C2D7FE5348E1B147BCA15975FBA2307501464272C9@US01WEMBX2.internal.synopsys.com>
 <1547553603.24248.49.camel@synopsys.com>
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On 1/15/19 4:00 AM, Eugeniy Paltsev wrote:=0A=
>>> -#ifdef PREALLOC_NOT_AVAIL=0A=
>>> -	prefetchw [r3, 64]	;Prefetch the next write location=0A=
>>> -#else=0A=
>>> -	prealloc  [r3, 64]=0A=
>>> -#endif=0A=
>>> +	PREALLOC_INSTR([r3, 64]) ;Prefetch the next write location=0A=
>> These are not solving the issue - I'd break this up and move these bits =
to your=0A=
>> next patch.=0A=
> Actually these are solving another issue - current implementation may cal=
l=0A=
> 'prealloc' instruction for L1 cache line which doesn't fully belongs to=
=0A=
> memeset area in case of 128B L1 D$ line length. As the 'prealloc' fill ca=
che line=0A=
> with zeros this leads to data corruption.=0A=
>=0A=
> So I would better keep these changes in this 'fix' patch.=0A=
=0A=
Fair enough. Although technically it is different bug which we haven't actu=
ally=0A=
hit, found by code review.=0A=
=0A=
> BTW, I've forgot again to add Cc: stable@vger.kernel.org, could you add i=
t for me,=0A=
> when applying patch?=0A=
> Thanks.=0A=
=0A=
Yes, I did that already !=0A=
=0A=
-Vineet=0A=