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Date:   Wed, 16 Jan 2019 15:45:47 +0100
From:   Boris Brezillon <bbrezillon@kernel.org>
To:     Peter Rosin <peda@axentia.se>
Cc:     Alexandre Belloni <alexandre.belloni@bootlin.com>,
        David Airlie <airlied@linux.ie>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        Boris Brezillon <boris.brezillon@bootlin.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Nicolas Ferre <nicolas.ferre@microchip.com>
Subject: Re: [PATCH 4/4] drm/atmel-hlcdc: do not immediately disable planes,
 wait for next frame
Message-ID: <20190116154547.711d7087@bbrezillon>
In-Reply-To: <e35d6894-fd62-efd1-38f7-cc5cbdbbacbb@axentia.se>
References: <20190110151020.30468-1-peda@axentia.se>
        <20190110151020.30468-5-peda@axentia.se>
        <20190110182904.5efd08f2@bbrezillon>
        <a31e6514-1643-9e47-cbb4-3323183fd370@axentia.se>
        <20190110202522.10206f2d@bbrezillon>
        <e35d6894-fd62-efd1-38f7-cc5cbdbbacbb@axentia.se>
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On Fri, 11 Jan 2019 14:29:28 +0000
Peter Rosin <peda@axentia.se> wrote:

> On 2019-01-10 20:25, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 18:51:21 +0000
> > Peter Rosin <peda@axentia.se> wrote:
> >   
> >> On 2019-01-10 18:29, Boris Brezillon wrote:  
> >>> On Thu, 10 Jan 2019 15:10:48 +0000
> >>> Peter Rosin <peda@axentia.se> wrote:
> >>>     
> >>>> The A2Q and UPDATE bits have no effect in the channel disable registers.
> >>>> However, since they are present, assume that the intention is to disable
> >>>> planes, not immediately as indicated by the RST bit, but on the next
> >>>> frame shift since that is what A2Q and UPDATE means in the channel enable
> >>>> registers.
> >>>>
> >>>> Disabling the plane on the next frame shift is done with the EN bit,
> >>>> so use that.    
> >>>
> >>> It's been a long time, but I think I had a good reason for forcing a
> >>> reset. IIRC, when you don't do that and the CRTC is disabled before the
> >>> plane, the EN bit stays around, and next time you queue a plane update,
> >>> you'll start with an invalid buf pointer.    
> >>
> >> It might be possible to clear the EN bit in ...CHDR before enabling the
> >> plane in ...CHER. Or is that too late?  
> > 
> > I think I tried that, but I'm not sure (BTW, this change was done in
> > bd4248bb5e8b ("drm: atmel-hlcdc: reset layer A2Q and UPDATE bits when  
> 
> That patch is a big fat NOP if you read the documentation. Those bits
> are marked with a '-' for all LCDC channel disable registers, for all
> supported chips IIUC. Are the effects of those bits mentioned in any
> errata?

IIRC, it was not documented in the datasheet, but this came out during
a discussion with the IP designer.

> 
> It would be good with a comment that the present undocumented disable
> method is intentional.

Yes, I should have added a comment about that, my bad.

> That would have kept me from assuming the whole
> thing was just copy-paste junk from ..._enable that happened to work.
> 
> >> disabling it")). Anyway, I'm not even sure this is still needed now
> >> that atomic updates have a wait_for_flip_done/vblank() in the commit
> >> path.  
> 
> The documentation for the RST bit states "Resets the layer immediately.
> The frame is aborted." which sounds a bit scary and heavy-handed. But
> again, I don't know what that actually means and what the effects are
> but that was the reason for me wanting to avoid the RST bit.

As I said, I'm not even sure the problem I was trying to fix still
exists.