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From:   Andy Lutomirski <luto@kernel.org>
Date:   Wed, 16 Jan 2019 15:51:16 -0800
Message-ID: <CALCETrWQMg8BEk4fZ5-GyP=VL2zEk_UQr67iQt-fqf4cC8nHcQ@mail.gmail.com>
Subject: Re: [PATCH v2 2/3] x86/umwait: Setup umwait C0.2 state
To:     Fenghua Yu <fenghua.yu@intel.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
        H Peter Anvin <hpa@zytor.com>,
        Andrew Cooper <andrew.cooper3@citrix.com>,
        Ashok Raj <ashok.raj@intel.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
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On Wed, Jan 16, 2019 at 1:24 PM Fenghua Yu <fenghua.yu@intel.com> wrote:
>
> UMWAIT or TPAUSE called by user process makes processor to reside in
> a light-weight power/performance optimized state (C0.1 state) or an
> improved power/performance optimized state (C0.2 state).
>
> IA32_UMWAIT_CONTROL MSR register allows OS to set global maximum umwait
> time and disable C0.2 on the processor.
>
> By default C0.2 is enabled so user wait instructions can enter the state
> if user wants to save more power but wakeup time is slower. In some cases
> e.g. real time, user wants to disable C0.2 and all C0.2 requests revert
> to C0.1.
>
> A new "/sys/devices/system/cpu/umwait_control/umwait_enable_c0_2" file is
> created to allow user to check if C0.2 is enabled or disabled and also
> allow user to enable or disable C0.2. Value "0" in the file means C0.2 is
> disabled. Value "1" means C0.2 is enabled.

Do you have any sense as to what the actual C0.2 entry and exit latency is?

--Andy