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[209.132.180.67]) by mx.google.com with ESMTP id c6si1363872plr.414.2019.01.17.03.45.07; Thu, 17 Jan 2019 03:45:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=fzhplasc; dkim=pass header.i=@codeaurora.org header.s=default header.b=fzhplasc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728243AbfAQJ1b (ORCPT + 99 others); Thu, 17 Jan 2019 04:27:31 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39266 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725965AbfAQJ1b (ORCPT ); Thu, 17 Jan 2019 04:27:31 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B1B0B6021A; Thu, 17 Jan 2019 09:27:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1547717250; bh=ha3EEdy0k9HNUff6t9j+eSO2ILmrLR5UiUWmfVUPmZU=; h=From:To:Cc:Subject:Date:From; b=fzhplasc4Y4ORa3iZsE/ePbnHcgfqWwcg7KIsaMuCiw1+SUToPN2y7oUwk8P/TxoC doNOyalIjRmYZ5Qel6UiCDCyS0X4bkz1ZZrAXyvNsqHz4UYVuNzpusuJyRjDe6cw1d K3rMBxczeJYJVCzI+Z+yUyX5RdInM0IYKTUk1T2c= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_INVALID,DKIM_SIGNED autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-41.ap.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3E25F6021A; Thu, 17 Jan 2019 09:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1547717250; bh=ha3EEdy0k9HNUff6t9j+eSO2ILmrLR5UiUWmfVUPmZU=; h=From:To:Cc:Subject:Date:From; b=fzhplasc4Y4ORa3iZsE/ePbnHcgfqWwcg7KIsaMuCiw1+SUToPN2y7oUwk8P/TxoC doNOyalIjRmYZ5Qel6UiCDCyS0X4bkz1ZZrAXyvNsqHz4UYVuNzpusuJyRjDe6cw1d K3rMBxczeJYJVCzI+Z+yUyX5RdInM0IYKTUk1T2c= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3E25F6021A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: will.deacon@arm.com, robin.murphy@arm.com, joro@8bytes.org, iommu@lists.linux-foundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, tfiga@chromium.org, Vivek Gautam Subject: [PATCH 0/2] iommu/arm: Add support for non-coherent page tables Date: Thu, 17 Jan 2019 14:57:16 +0530 Message-Id: <20190117092718.1396-1-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 2.16.1.72.g5be1f00a9a70 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As discussed in the Qcom system cache support thread [1], it is imperative that we enable the support for non-cacheable page tables for SMMU implementations for which removing snoop latency on walks by making mappings as non-cacheable, outweighs the cost of cache maintenance on PTE updates. This series adds a new SMMU device tree option to let the particular SMMU configuration setup cacheable or non-cacheable mappings for page-tables out of box. We set a new quirk for i/o page tables - IO_PGTABLE_QUIRK_NON_COHERENT, that lets us set different TCR configurations. This quirk enables the non-cacheable page tables for all masters sitting on SMMU. Should this control be available per smmu_domain as each master may have a different perf requirement? Enabling this for the entire SMMU may not be desirable for all masters. [1] https://lore.kernel.org/patchwork/patch/1020906/ Vivek Gautam (2): iommu/io-pgtable-arm: Add support for non-coherent page tables iommu/arm-smmu: Add support for non-coherent page table mappings drivers/iommu/arm-smmu.c | 7 +++++++ drivers/iommu/io-pgtable-arm.c | 17 ++++++++++++----- drivers/iommu/io-pgtable.h | 6 ++++++ 3 files changed, 25 insertions(+), 5 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation