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Message-ID: <1547820733.2626.11.camel@pengutronix.de>
Subject: Re: [PATCH 1/2] ARM: dts: imx6q: add pmu interrupt-affinity
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Stefan Agner <stefan@agner.ch>, shawnguo@kernel.org,
        s.hauer@pengutronix.de
Cc:     max.krummenacher@toradex.com, marcel.ziswiler@toradex.com,
        linux-kernel@vger.kernel.org, linux-imx@nxp.com,
        kernel@pengutronix.de, fabio.estevam@nxp.com, dev@pschenker.ch,
        linux-arm-kernel@lists.infradead.org
Date:   Fri, 18 Jan 2019 15:12:13 +0100
In-Reply-To: <20190118135907.2336-1-stefan@agner.ch>
References: <20190118135907.2336-1-stefan@agner.ch>
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Am Freitag, den 18.01.2019, 14:59 +0100 schrieb Stefan Agner:
> Explicitly specify interrupt affinity to avoid HW perfevents
> need to guess. This avoids the following error upon boot:
>   hw perfevents: no interrupt-affinity property for /pmu, guessing.
> 
But then it isn't correct either AFAICS. On i.MX6 all the PMU IRQs are
ORed together into a single SPI, instead of each core dealing with its
own PPI. So pretending that there are more IRQs with affinity to each
core isn't the right thing to do, no?

Regards,
Lucas

> Specifying all four CPUs shows no aversive effects on i.MX 6Dual
> SoCs.
> 
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  arch/arm/boot/dts/imx6q.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 8381d24eff7d..d2c1977c8b16 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -537,6 +537,13 @@
> >  			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
>  };
>  
> +&pmu {
> > > +	interrupt-affinity = <&{/cpus/cpu@0}>,
> > > +			     <&{/cpus/cpu@1}>,
> > > +			     <&{/cpus/cpu@2}>,
> > > +			     <&{/cpus/cpu@3}>;
> +};
> +
>  &vpu {
> >  	compatible = "fsl,imx6q-vpu", "cnm,coda960";
>  };