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[209.132.180.67]) by mx.google.com with ESMTP id az5si9282297plb.166.2019.01.20.03.33.41; Sun, 20 Jan 2019 03:33:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730541AbfATLch (ORCPT + 99 others); Sun, 20 Jan 2019 06:32:37 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49240 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730492AbfATLch (ORCPT ); Sun, 20 Jan 2019 06:32:37 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 814C5A78; Sun, 20 Jan 2019 03:32:36 -0800 (PST) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8F80A3F557; Sun, 20 Jan 2019 03:32:32 -0800 (PST) Date: Sun, 20 Jan 2019 11:32:29 +0000 Message-ID: <86imyja7jm.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Brian Masney Cc: linus.walleij@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, andy.gross@linaro.org, shawnguo@kernel.org, dianders@chromium.org, linux-gpio@vger.kernel.org, nicolas.dechesne@linaro.org, niklas.cassel@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 07/15] qcom: spmi-gpio: add support for hierarchical IRQ chip In-Reply-To: <20190119204252.18370-8-masneyb@onstation.org> References: <20190119204252.18370-1-masneyb@onstation.org> <20190119204252.18370-8-masneyb@onstation.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 19 Jan 2019 20:42:44 +0000, Brian Masney wrote: > > spmi-gpio did not have any irqchip support so consumers of this in > device tree would need to call gpio[d]_to_irq() in order to get the > proper IRQ on the underlying PMIC. IRQ chips in device tree should > be usable from the start without the consumer having to make an > additional call to get the proper IRQ on the parent. This patch adds > hierarchical IRQ chip support to the spmi-gpio code to correct this > issue. > > Driver was tested using the volume buttons (via gpio-keys) on the LG > Nexus 5 (hammerhead) phone with the following two configurations. > > volume-up { > interrupts-extended = <&pm8941_gpios 2 IRQ_TYPE_EDGE_BOTH>; > ... > }; > > volume-up { > gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; > ... > }; > > Both configurations now show that spmi-gpio is the IRQ domain and that > the IRQ is setup in a hierarchy. > > $ grep volume_up /proc/interrupts > 72: 6 0 spmi-gpio 1 Edge volume_up > > $ cat /sys/kernel/debug/irq/irqs/72 > handler: handle_edge_irq > device: (null) > status: 0x00000403 > _IRQ_NOPROBE > istate: 0x00000000 > ddepth: 0 > wdepth: 0 > dstate: 0x02400203 > IRQ_TYPE_EDGE_RISING > IRQ_TYPE_EDGE_FALLING > IRQD_ACTIVATED > IRQD_IRQ_STARTED > node: 0 > affinity: 0-3 > effectiv: > domain: :soc:spmi@fc4cf000:pm8941@0:gpios@c000 > hwirq: 0x1 > chip: spmi-gpio > flags: 0x4 > IRQCHIP_MASK_ON_SUSPEND > parent: > domain: :soc:spmi@fc4cf000 > hwirq: 0xc100057 > chip: pmic_arb > flags: 0x4 > IRQCHIP_MASK_ON_SUSPEND > > Signed-off-by: Brian Masney > Reviewed-by: Stephen Boyd > --- > Changes since v5: > - Change IRQ_TYPE_NONE to IRQ_TYPE_EDGE_RISING > > Changes since v4: > - None > > Changes since v3: > - None > > Changes since v2: > - Use PMIC_GPIO_PHYSICAL_OFFSET instead of the 1 constant > - Use gpiochip_irq_domain_{activate,deactivate} > - Changed 'fwspec->param[0] + 0xc0 - 1' to 'hwirq + c0' in call to > irq_domain_alloc_irqs_parent > > Changes since v1: > - Use two cells for interrupts instead of four. > - Pin numbers in interrupts-extended are now one based instead of zero > based so that they match the GPIO pin number. > - Drop unnecessary parenthesis in pmic_gpio_domain_translate > - Add missing of_node_put() > - Remove irq field from pmic_gpio_pad struct that is no longer > necessary. > > drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 115 +++++++++++++++++++++-- > 1 file changed, 105 insertions(+), 10 deletions(-) Reviewed-by: Marc Zyngier Thanks, M. -- Jazz is not dead, it just smell funny.