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[209.132.180.67]) by mx.google.com with ESMTP id c10si11797637pll.271.2019.01.20.23.13.38; Sun, 20 Jan 2019 23:13:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=BZDt5m8Z; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726125AbfAUHLB (ORCPT + 99 others); Mon, 21 Jan 2019 02:11:01 -0500 Received: from condef-06.nifty.com ([202.248.20.71]:33850 "EHLO condef-06.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725871AbfAUHLA (ORCPT ); Mon, 21 Jan 2019 02:11:00 -0500 Received: from conuserg-07.nifty.com ([10.126.8.70])by condef-06.nifty.com with ESMTP id x0L6XASA002631 for ; Mon, 21 Jan 2019 15:33:10 +0900 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id x0L6WCPC003098; Mon, 21 Jan 2019 15:32:13 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com x0L6WCPC003098 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1548052333; bh=qrh/ZcVeEBRczMZx/DNnPsCU/3ppDsvTOZXlUv3uS90=; h=From:To:Cc:Subject:Date:From; b=BZDt5m8ZX+oGTcNyNLj6dly8ZyqgwpbvGocWGu5X8myzZosRQGKmXE5hp+6CFcyKG sjovxM/VtDF+Pqe3U4dDOQ7JDYm/cKuuoLElr4hb36/B3w2Rn1avvFPB8jesJzrEbU enEuwao6qwfXcErDo18UjbMFYRaCQVQQ8yHVsb7S4yIkJ5RvcRFRKg5fj6oKNoVnVg 2CXMYsZuKTCMMJlBJRKFqZTlXMZj/2bW8AmABLpwuui0EwyEa5DsEbiYZLVPu7iVAf xTWhyFyiTdx6DANV8NzwxZHAnnK+4VVG5qwIk+TjPcfA3SNu275K658A7MzyNA7xqT j/BgSva9Sjv+w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org, Boris Brezillon , Miquel Raynal Cc: Masahiro Yamada , Brian Norris , linux-kernel@vger.kernel.org, Marek Vasut , Richard Weinberger , David Woodhouse , Boris Brezillon Subject: [PATCH v2] mtd: rawnand: remove ->legacy.erase and single_erase() Date: Mon, 21 Jan 2019 15:32:07 +0900 Message-Id: <1548052327-26483-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the last user of this hook, denali.c, stopped using it, we can remove the erase hook from nand_legacy. I squashed single_erase() because only the difference between single_erase() and nand_erase_op() is the number of bit shifts. The status/ret conversion in nand_erase_nand() is unneeded since commit eb94555e9e97 ("mtd: nand: use usual return values for the ->erase() hook"). Cleaned it up now. Signed-off-by: Masahiro Yamada --- This depends on the denali patch: http://patchwork.ozlabs.org/patch/1028264/ Changes in v2: - I noticed the masking by chip->pagemask is still needed drivers/mtd/nand/raw/nand_base.c | 31 ++++--------------------------- include/linux/mtd/rawnand.h | 2 -- 2 files changed, 4 insertions(+), 29 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index cca4b24..7ea3f10 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4155,23 +4155,6 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to, } /** - * single_erase - [GENERIC] NAND standard block erase command function - * @chip: NAND chip object - * @page: the page address of the block which will be erased - * - * Standard erase command for NAND chips. Returns NAND status. - */ -static int single_erase(struct nand_chip *chip, int page) -{ - unsigned int eraseblock; - - /* Send commands to erase a block */ - eraseblock = page >> (chip->phys_erase_shift - chip->page_shift); - - return nand_erase_op(chip, eraseblock); -} - -/** * nand_erase - [MTD Interface] erase block(s) * @mtd: MTD device structure * @instr: erase instruction @@ -4194,7 +4177,7 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, int allowbbt) { - int page, status, pages_per_block, ret, chipnr; + int page, pages_per_block, ret, chipnr; loff_t len; pr_debug("%s: start = 0x%012llx, len = %llu\n", @@ -4246,17 +4229,11 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, (page + pages_per_block)) chip->pagebuf = -1; - if (chip->legacy.erase) - status = chip->legacy.erase(chip, - page & chip->pagemask); - else - status = single_erase(chip, page & chip->pagemask); - - /* See if block erase succeeded */ - if (status) { + ret = nand_erase_op(chip, (page & chip->pagemask) >> + (chip->phys_erase_shift - chip->page_shift)); + if (ret) { pr_debug("%s: failed erase, page 0x%08x\n", __func__, page); - ret = -EIO; instr->fail_addr = ((loff_t)page << chip->page_shift); goto erase_exit; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 33e240a..5e37534 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -936,7 +936,6 @@ static inline void nand_controller_init(struct nand_controller *nfc) * @waitfunc: hardware specific function for wait on ready. * @block_bad: check if a block is bad, using OOB markers * @block_markbad: mark a block bad - * @erase: erase function * @set_features: set the NAND chip features * @get_features: get the NAND chip features * @chip_delay: chip dependent delay for transferring data from array to read @@ -962,7 +961,6 @@ struct nand_legacy { int (*waitfunc)(struct nand_chip *chip); int (*block_bad)(struct nand_chip *chip, loff_t ofs); int (*block_markbad)(struct nand_chip *chip, loff_t ofs); - int (*erase)(struct nand_chip *chip, int page); int (*set_features)(struct nand_chip *chip, int feature_addr, u8 *subfeature_para); int (*get_features)(struct nand_chip *chip, int feature_addr, -- 2.7.4