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Date:   Wed, 23 Jan 2019 16:48:02 +0000
From:   Mark Rutland <mark.rutland@arm.com>
To:     Pramod Kumar <pramod.kumar@broadcom.com>
Cc:     Sudeep Holla <sudeep.holla@arm.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will.deacon@arm.com>,
        Suzuki K Poulose <Suzuki.Poulose@arm.com>,
        Dave Martin <dave.martin@arm.com>,
        Rob Herring <robh@kernel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Steve Capper <steve.capper@arm.com>,
        BCM Kernel Feedback <bcm-kernel-feedback-list@broadcom.com>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC 1/1] arm64: Use PSCI calls for CPU stop when hotplug
 is supported
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On Mon, Jan 21, 2019 at 11:30:02AM +0530, Pramod Kumar wrote:
> On Mon, Jan 21, 2019 at 11:28 AM Pramod Kumar <pramod.kumar@broadcom.com>
> wrote:
> 
>     Need comes from a specific use case where one Accelerator card(SoC) is
>     plugged in a sever over a PCIe interface.  This Card gets supply from a
>     battery, which could provide very less power for a very small time, in case
>     of any power loss. Once Card switches to battery, this has to reduce its
>     power consumption to its lowest point and back-up the DDR contents asap
>     before battery gets fully drained off. 

In this example is Linux running on the server, or on the accelerator?

What precisely are you trying to back up from DDR, and why?

What is responsible for backing up that contents?

>     Since battery can provide limited power for a very short time hence need to
>     transition to lowest power. As per the transition process , CPUs power
>     domain has to be off but before that it needs to flush out its content to
>     system memory(L3) so that content could be backed-up by a MCU, a controller
>     consuming very less power. Since we can not afford plugging-out every
>     individual CPUs in sequence hence uses  ipi_cpu_stop for all other CPUs
>     which ultimately switch to ATF to flush out all the CPUs caches and comes
>     out of coherency domain so that its power rails could be switched-off.

If you're stopping CPUs from completely arbitrary states, what is the
benefit of saving the RAM contents?

CPUs might be running with IRQs disabled for an arbitrarily long time,
so there's no guarantee that all of them will be turned off before power
is lost.

I'm very confused as to what you're trying to achieve here.

Thanks,
Mark.