Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp2015884imu; Thu, 24 Jan 2019 06:00:01 -0800 (PST) X-Google-Smtp-Source: ALg8bN6xRmxmTv89TSiO7/KTxU91p0OjhyCpAswrmQUGXenuLUNeRlriTKOiOvG1GxmDgE6pe82T X-Received: by 2002:a17:902:503:: with SMTP id 3mr6705732plf.233.1548338401758; Thu, 24 Jan 2019 06:00:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548338401; cv=none; d=google.com; s=arc-20160816; b=Iw9DWrmlD4RskbgTr3vBPf7oMrqI2zFdIdMN4TqYgFhOS5VwH/FDaGAteAMxJqtnV9 AdE6ijpQfJ14ERvEvxgXgj9J8/HPhHA6belj+XoF3+XK4XOaFZStaetn0pQreT3lzt/x PiQXjy2/fUDBlccVtttoZZ0GtDP9Tv48OWV3VT2c4IQ+tJlXHPL2ZBPhr0HUxMKBwXkt 8DztxnLDwzaq7BM9LuTBXqM63sSHFG/S12zwcTYKI8ChcjgodHtA3JiTC+C1WgqLLyi2 07yqaA79mGi1KvH7vUe9zx41F040Wjuvp3zuArBWcCLrwQCH6Dyo70KYjHsc5I/l97e7 nrEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=xNjDaNA03H6AQxVROUao/6yiuQCiOm2CI9O0MPZSzJk=; b=YJ3D2Y9rfvhn1LRGOn0biBs6iEZkA3clItXmlWNJWxA9WN4beSVQdNy38JT0vStcd2 UcILe/Gsa+AHGH+kJAUz13Pyv+hkUqaOXjWKvDphJ1sm/WMt2m8u+1Qqt6PtVajVRqyL LHiRmWmnFQ0YNh9HX1vYBdOvmTq9n/fPuKzBs7zC1Onta8daVKpIgwGGfjI6qSOvGh1W 0nwfnLev5OEPTUpYrC/686PCG41P/DXsGoUXb6uX21XPYavyX/lYLNW6dYu/Ob63++Mi fwzNpWp4lsmXC2DGUgjVeKoFCILRhdRG9u4kELnKBhXJRFhI2FY7gIrDqYIeKwKyO1i/ ZV6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u72si6969898pgc.360.2019.01.24.05.59.45; Thu, 24 Jan 2019 06:00:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728031AbfAXN7k (ORCPT + 99 others); Thu, 24 Jan 2019 08:59:40 -0500 Received: from unicorn.mansr.com ([81.2.72.234]:51430 "EHLO unicorn.mansr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727596AbfAXN7j (ORCPT ); Thu, 24 Jan 2019 08:59:39 -0500 X-Greylist: delayed 445 seconds by postgrey-1.27 at vger.kernel.org; Thu, 24 Jan 2019 08:59:39 EST Received: by unicorn.mansr.com (Postfix, from userid 51770) id 9032015AC5; Thu, 24 Jan 2019 13:52:13 +0000 (GMT) From: Mans Rullgard To: Johan Hovold Cc: Greg Kroah-Hartman , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] USB: serial: cp210x: support all gpios on CP2102N QFN28 package Date: Thu, 24 Jan 2019 13:48:39 +0000 Message-Id: <20190124134839.13316-1-mans@mansr.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QFN28 package version of the CP2102N has three additional gpio pins. Add support for these. Signed-off-by: Mans Rullgard --- drivers/usb/serial/cp210x.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index c0777a374a88..336a3c0f9f2c 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -1574,12 +1574,6 @@ static int cp2102n_gpioconf_init(struct usb_serial *serial) if (config_version != 0x01) return -ENOTSUPP; - /* - * We only support 4 GPIOs even on the QFN28 package, because - * config locations of GPIOs 4-6 determined using reverse - * engineering revealed conflicting offsets with other - * documented functions. So we'll just play it safe for now. - */ priv->gc.ngpio = 4; /* @@ -1594,6 +1588,19 @@ static int cp2102n_gpioconf_init(struct usb_serial *serial) /* 0 indicates GPIO mode, 1 is alternate function */ priv->gpio_altfunc = (gpio_ctrl >> 2) & 0x0f; + if (priv->partnum == CP210X_PARTNUM_CP2102N_QFN28) { + /* + * For the QFN28 package, GPIO4-6 are controlled by + * the low three bits of the mode/latch fields. + * Contrary to the document linked above, the bits for + * the SUSPEND pins are elsewhere. No alternate + * function is available for these pins. + */ + priv->gc.ngpio = 7; + gpio_latch |= (gpio_rst_latch & 7) << 4; + priv->gpio_pushpull |= (gpio_pushpull & 7) << 4; + } + /* * The CP2102N does not strictly has input and output pin modes, * it only knows open-drain and push-pull modes which is set at -- 2.20.1