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[209.132.180.67]) by mx.google.com with ESMTP id p5si12846190pls.338.2019.01.25.00.44.58; Fri, 25 Jan 2019 00:45:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f1ggZk85; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727996AbfAYInU (ORCPT + 99 others); Fri, 25 Jan 2019 03:43:20 -0500 Received: from mail-io1-f68.google.com ([209.85.166.68]:46401 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726200AbfAYInT (ORCPT ); Fri, 25 Jan 2019 03:43:19 -0500 Received: by mail-io1-f68.google.com with SMTP id s8so7085133iob.13 for ; Fri, 25 Jan 2019 00:43:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=5C27t5i/Kxs7sqw0V4cwfbsTRjCbPSa4Pe/4IHFM4IU=; b=f1ggZk859V6w+zigTYcibT8r3QHPSARkxS5C9jTf8Sm2bH8BmAd0PedGXdK0Jc6EHp yrxCRVZfrGCkCosLH5cD7gD4aEqBABGyzT4GMdU0JmcXZIeCqUWCdwYS67AIFos/X6N9 /Zc7r7Bogu+Zx0ac2BDv9+u0w22QbsOHfWPVE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=5C27t5i/Kxs7sqw0V4cwfbsTRjCbPSa4Pe/4IHFM4IU=; b=N+sCrkZgWS1DF6bgVJL72kbuz8+S+PDp5GeJBVPg3JjP6a1mwPszAb2wEfTRhsMuKx xSPf4bahKlPBBQy6rZnDjgFYWkwLxr/PrnsNt4SCmsgjTxcf4hrxfog5s4iNs2iowGns IbpZmuyY45lx1A9DbK/Zk/BgbW+ytyyz+Bs8iO+421nbZW5sJW56vT3fcKYXFStA25hJ ld18GZjkwkxGgKvg+WHYlUd1fyfIiopLb0Gh030MhYrM7gSc/IR2rSVLMPagDEy0+e4o pw/OAh5QmCdlZBBG2hSXG2l0kPWRS1ni5KvHAHWa14M9HNSmNHhO1GV2PKMcjun8TwZJ TxBg== X-Gm-Message-State: AHQUAua+7IXFDV0ZNPllEvV5UNZ+whh2JvtP0lcS+bGc5iBE8+IKylaL MebnOGv0rt+0nUci9kwJ5ookJZFtUDfpbLiqHpAmtw== X-Received: by 2002:a5d:8410:: with SMTP id i16mr5987962ion.173.1548405798631; Fri, 25 Jan 2019 00:43:18 -0800 (PST) MIME-Version: 1.0 References: <20190124120658.30288-1-ard.biesheuvel@linaro.org> <3cca35a9-c71c-a100-b29d-31ba0d1d10b1@amd.com> In-Reply-To: From: Ard Biesheuvel Date: Fri, 25 Jan 2019 09:43:07 +0100 Message-ID: Subject: Re: [PATCH] drm: enable uncached DMA optimization for ARM and arm64 To: Alex Deucher Cc: "Koenig, Christian" , "Zhou, David(ChunMing)" , Maxime Ripard , Benjamin Herrenschmidt , Carsten Haitzler , David Airlie , Maarten Lankhorst , dri-devel , "Daenzer, Michel" , "linux-kernel@vger.kernel.org" , Will Deacon , Christoph Hellwig , "Zhang, Jerry" , "Huang, Ray" , amd-gfx list , Daniel Vetter , Michael Ellerman , "Deucher, Alexander" , Sean Paul , "linux-arm-kernel@lists.infradead.org" , Robin Murphy Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote: > > On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel > wrote: > > > > On Thu, 24 Jan 2019 at 13:31, Koenig, Christian > > wrote: > > > > > > Am 24.01.19 um 13:06 schrieb Ard Biesheuvel: > > > > The DRM driver stack is designed to work with cache coherent device= s > > > > only, but permits an optimization to be enabled in some cases, wher= e > > > > for some buffers, both the CPU and the GPU use uncached mappings, > > > > removing the need for DMA snooping and allocation in the CPU caches= . > > > > > > > > The use of uncached GPU mappings relies on the correct implementati= on > > > > of the PCIe NoSnoop TLP attribute by the platform, otherwise the GP= U > > > > will use cached mappings nonetheless. On x86 platforms, this does n= ot > > > > seem to matter, as uncached CPU mappings will snoop the caches in a= ny > > > > case. However, on ARM and arm64, enabling this optimization on a > > > > platform where NoSnoop is ignored results in loss of coherency, whi= ch > > > > breaks correct operation of the device. Since we have no way of > > > > detecting whether NoSnoop works or not, just disable this > > > > optimization entirely for ARM and arm64. > > > > > > > > Cc: Christian Koenig > > > > Cc: Alex Deucher > > > > Cc: David Zhou > > > > Cc: Huang Rui > > > > Cc: Junwei Zhang > > > > Cc: Michel Daenzer > > > > Cc: David Airlie > > > > Cc: Daniel Vetter > > > > Cc: Maarten Lankhorst > > > > Cc: Maxime Ripard > > > > Cc: Sean Paul > > > > Cc: Michael Ellerman > > > > Cc: Benjamin Herrenschmidt > > > > Cc: Will Deacon > > > > Cc: Christoph Hellwig > > > > Cc: Robin Murphy > > > > Cc: amd-gfx list > > > > Cc: dri-devel > > > > Reported-by: Carsten Haitzler > > > > Signed-off-by: Ard Biesheuvel > > > > > > The subject line should probably read "disable uncached...". > > > > > > > Ugh, of course ... > > > > > With that fixed the patch is Reviewed-by: Christian K=C3=B6nig > > > . > > > > > Same: > Reviewed-by: Alex Deucher > Thanks all Should I resend the patch with the subject corrected?