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[209.132.180.67]) by mx.google.com with ESMTP id u30si33647051pgn.170.2019.01.28.06.17.51; Mon, 28 Jan 2019 06:18:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MPMr7hVo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726829AbfA1ORh (ORCPT + 99 others); Mon, 28 Jan 2019 09:17:37 -0500 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33212 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726682AbfA1ORh (ORCPT ); Mon, 28 Jan 2019 09:17:37 -0500 Received: by mail-lj1-f193.google.com with SMTP id v1-v6so14399337ljd.0 for ; Mon, 28 Jan 2019 06:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pnCwQx8NoJkUd1q9lUiNxR5g2FVyPHrO2YY/Ijat5fE=; b=MPMr7hVoeNRiaDaK5D1ei2FIt2O39HxW1zDfWzRmUtgVhS39lwGblZmx1DSFnqXNZn vS1ZYnXiXk0HZ62JXi1kNIyTqJYwaqeaLCzW2Q5CDQGpBy+dgclptEpe95RGnNzb8Cdn Njx5/cLuhHxynOv4Z8TbV1D547KGmtm5+rd80= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=pnCwQx8NoJkUd1q9lUiNxR5g2FVyPHrO2YY/Ijat5fE=; b=RWtzD1USSy31sZYHdVswAKx/VkV5gAwcaaOU1n5cu9GsPomzINZsvq8dVg7z3lSOXP qQIGCukL2NCwWwwYIXb8nzTUTezM0+oMVSf/ac8x77+lNwbhEp68SqnP8RrN+ukpM1xk 6O1Ycdys73L/Jj97tii71WwvwfUjdmdFUCDNYKrzgY95+KrdH4KZB64Nv1JWa8trmQdJ 1trEdGv3J0m7P7b5OH1NtkvOINQgJnR6c1fecaNl8ei01HNuscciL/YCy4CrLpbYfSZT J7GG8n6rv6RwsAM5LaazwrTbnajbtoVwHPe5hqXnn2oar/zFTkVEHvcqXAq2aa6Gwdw9 F9pQ== X-Gm-Message-State: AJcUuke63nw+0rOuILrOJwv+FNwsB1btOm1hIvHjtBVzWvh8PRfejzCw dtx3WdSx2KqWt4vkQ3S0grR1kFQzaP9cd+RQcQH0pw== X-Received: by 2002:a2e:131a:: with SMTP id 26-v6mr16801786ljt.107.1548685055127; Mon, 28 Jan 2019 06:17:35 -0800 (PST) MIME-Version: 1.0 References: <20190124202205.7940-1-ilina@codeaurora.org> In-Reply-To: <20190124202205.7940-1-ilina@codeaurora.org> From: Linus Walleij Date: Mon, 28 Jan 2019 15:17:22 +0100 Message-ID: Subject: Re: [PATCH v2 0/8] qcom: support wakeup capable GPIOs To: Lina Iyer Cc: Stephen Boyd , Evan Green , Marc Zyngier , "linux-kernel@vger.kernel.org" , rplsssn@codeaurora.org, linux-arm-msm@vger.kernel.org, "thierry.reding@gmail.com" , Bjorn Andersson , Doug Anderson Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 24, 2019 at 9:22 PM Lina Iyer wrote: > This is a bug fix submission of the v1 posted here [1]. The discussion on how > to represent the wakeup-parent interrupt controller is on-going [2] here. The > reiew comments in [1], from Doug and Stephen are addressed in this patch. > > The series attempts to add GPIO chip in hierarchy with PDC interrupt controller > that can detect and wakeup the GPIOs routed to it, when the system is > suspend/deep sleep mode. I kind of start to get the hang of this now. This is starting to look finished. Some words on the hierarchical GPIO IRQs: I have started to look into hierarchical GPIO+irqchip since the usage of such is spreading. I have been on to Thierry patches trying to make him implement more generic helpers in the gpiolib irqchip library functions. In short I see the following: - Hierarchical gpiochips all have .alloc() and .translate() functions that look more or less the same. - They all fall down to remapping either tuples or entire ranges of IRQs from parent to child with a linear look-up table on allocation. So my idea would be to add support for this into the gpiolib hierarchical irqchip helper: by supplying a parent irqdomain and a list of translation tuples, we should be able to handle pretty much any hierarchical GPIO irqdomain (famous last words). Right now I am converting the IXP4xx platform to hierarchical IRQ from the ground up (it is not even using device tree so it is a bit of a challenge) but it seems to be working. So I will try to post this in some hopefully working form, and on top of those changes or before them introduce some helpers in the core for hierarchical irqs. Or I fail. Anyways, I do not think my ambitions for refactoring the helpers can stand in the way of support for these use cases and new hardware, so maybe we need to merge a few more hierarchical drivers just bypassing the gpiolib helpers. I don't want to block development, and I suspect Thierry might be getting annoyed at me at this point, so we should maybe just pile up a few more hierarchical chips so I can refactor them later. What do you think? Yours, Linus Walleij