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Date:   Mon, 28 Jan 2019 08:27:21 -0800
From:   Christoph Hellwig <hch@infradead.org>
To:     Thomas Bogendoerfer <tbogendoerfer@suse.de>
Cc:     Christoph Hellwig <hch@infradead.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        James Hogan <jhogan@kernel.org>, linux-kernel@vger.kernel.org,
        linux-mips@vger.kernel.org, linux-pci@vger.kernel.org,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Paul Burton <paul.burton@mips.com>,
        Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge
Message-ID: <20190128162721.GA25378@infradead.org>
References: <20190124174728.28812-1-tbogendoerfer@suse.de>
 <20190124174728.28812-8-tbogendoerfer@suse.de>
 <20190128133317.GD744@infradead.org>
 <20190128150135.66f85834ab80813e6dc5ddf5@suse.de>
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On Mon, Jan 28, 2019 at 03:01:35PM +0100, Thomas Bogendoerfer wrote:
> On Mon, 28 Jan 2019 05:33:17 -0800
> Christoph Hellwig <hch@infradead.org> wrote:
> 
> > Shouldnt this just use chained irqchip drivers instead?
> 
> you mean using irq_set_chained_handler() ? If yes, this IMHO doesn't look usefull
> because it's used for adding a secondary interrupt controller. But what I need
> is telling bridge ASIC to direct the xtalk IRQ packet to a specific HUB/HEART/BEDROCK
> from the HUB/HEART/BEDROCK specific code. And want to avoid dragging in bridge details
> to that specific code.

Yes, but don't we have nested interrupt controllers here?  Even if they
don't really do much in the fast path the setup does look chained to me.
Then again I'm not really an expert in the irq handling code nor in this
hardware, so maybe Thomas or Marc might have a better idea.