Received: by 2002:ad5:474a:0:0:0:0:0 with SMTP id i10csp4069281imu; Mon, 28 Jan 2019 16:40:38 -0800 (PST) X-Google-Smtp-Source: ALg8bN6x4fIez/+aeXOmI9qRM5pUO/oIjiyss+xNtkJNf7wCFdsGf3s+lNXAynIz//4AScTmsohx X-Received: by 2002:a17:902:2862:: with SMTP id e89mr24296320plb.158.1548722438029; Mon, 28 Jan 2019 16:40:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548722438; cv=none; d=google.com; s=arc-20160816; b=KXYKw9khP3RQlQRThs6QJ60Iqel+lRe+Y1nrxD+BFu978OdhGcRgOERk1azZr42wn0 YdI+2olnhze9KXl7ekZQX2hAxLFR3KTHrBcKLmHepwxK9n2N4q+tNjmkF+YZgFx/6hjF ZPDHdK9IPk5t2weRQVFnLIUTEDFEKuXXg2JhVlpv9CuonYCWIIOKM9BZKcBvISmJIjXu V6rbe8aGjqwIdEc6mVbLw/lzRXe7If71aaiiwDtFAa76KRX/WNZjijWWkcAyQGiOI6AC UiC5+jEjy2lXc0U+2g2loFKj4ACzVxnyQ2oQkaAHdx1+o7e8H4HwuDct4HpkBiPsoorZ +/sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=6v9W4vLv93QaEUNRE1Az/Zy+/uNslS9lkuxp7pzJKCg=; b=N/VjF2KMZ3iaRR1XchCholEYXVTfTxXnqqSUOCa3ymqjI1GxqWxjbHFdSSIABFklhQ QdMzqTic19K7Yye8NiBdgIhjiNWkZP2oEu3jEdjmqOrV7rlYnbX9wkq2mMyO1UOUoT8C mzm7H1WhSZDMKKX8wwGneg+Zd2xsxewL+HGzZdkje+99YF5HTrd4Xi1w8ErVtVEoDbvx N/aSs2eAhni4qMBGMb3zQLeEhrf1ug84vI2inQvdzTECqDJoIcIUDExFJm3+bPAx9zlt Zs4mEjDA90lANQJ00sATA+QZUiw0azNNLvbsSeGQh/nS/Jh0OEc0GXcWzvdUOgcmEE6j jI+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r17si21221573pls.380.2019.01.28.16.40.22; Mon, 28 Jan 2019 16:40:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727745AbfA2AjY (ORCPT + 99 others); Mon, 28 Jan 2019 19:39:24 -0500 Received: from mga06.intel.com ([134.134.136.31]:5081 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727304AbfA2AjN (ORCPT ); Mon, 28 Jan 2019 19:39:13 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jan 2019 16:39:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,535,1539673200"; d="scan'208";a="133921891" Received: from rpedgeco-desk5.jf.intel.com ([10.54.75.79]) by orsmga001.jf.intel.com with ESMTP; 28 Jan 2019 16:39:11 -0800 From: Rick Edgecombe To: Andy Lutomirski , Ingo Molnar Cc: linux-kernel@vger.kernel.org, x86@kernel.org, hpa@zytor.com, Thomas Gleixner , Borislav Petkov , Nadav Amit , Dave Hansen , Peter Zijlstra , linux_dti@icloud.com, linux-integrity@vger.kernel.org, linux-security-module@vger.kernel.org, akpm@linux-foundation.org, kernel-hardening@lists.openwall.com, linux-mm@kvack.org, will.deacon@arm.com, ard.biesheuvel@linaro.org, kristen@linux.intel.com, deneen.t.dock@intel.com, Kees Cook , Dave Hansen , Nadav Amit , Rick Edgecombe Subject: [PATCH v2 03/20] x86/mm: temporary mm struct Date: Mon, 28 Jan 2019 16:34:05 -0800 Message-Id: <20190129003422.9328-4-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129003422.9328-1-rick.p.edgecombe@intel.com> References: <20190129003422.9328-1-rick.p.edgecombe@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andy Lutomirski Sometimes we want to set a temporary page-table entries (PTEs) in one of the cores, without allowing other cores to use - even speculatively - these mappings. There are two benefits for doing so: (1) Security: if sensitive PTEs are set, temporary mm prevents their use in other cores. This hardens the security as it prevents exploding a dangling pointer to overwrite sensitive data using the sensitive PTE. (2) Avoiding TLB shootdowns: the PTEs do not need to be flushed in remote page-tables. To do so a temporary mm_struct can be used. Mappings which are private for this mm can be set in the userspace part of the address-space. During the whole time in which the temporary mm is loaded, interrupts must be disabled. The first use-case for temporary PTEs, which will follow, is for poking the kernel text. [ Commit message was written by Nadav ] Cc: Kees Cook Cc: Dave Hansen Acked-by: Peter Zijlstra (Intel) Reviewed-by: Masami Hiramatsu Tested-by: Masami Hiramatsu Signed-off-by: Andy Lutomirski Signed-off-by: Nadav Amit Signed-off-by: Rick Edgecombe --- arch/x86/include/asm/mmu_context.h | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 19d18fae6ec6..cd0c29e494a6 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -356,4 +356,36 @@ static inline unsigned long __get_current_cr3_fast(void) return cr3; } +typedef struct { + struct mm_struct *prev; +} temporary_mm_state_t; + +/* + * Using a temporary mm allows to set temporary mappings that are not accessible + * by other cores. Such mappings are needed to perform sensitive memory writes + * that override the kernel memory protections (e.g., W^X), without exposing the + * temporary page-table mappings that are required for these write operations to + * other cores. + * + * Context: The temporary mm needs to be used exclusively by a single core. To + * harden security IRQs must be disabled while the temporary mm is + * loaded, thereby preventing interrupt handler bugs from override the + * kernel memory protection. + */ +static inline temporary_mm_state_t use_temporary_mm(struct mm_struct *mm) +{ + temporary_mm_state_t state; + + lockdep_assert_irqs_disabled(); + state.prev = this_cpu_read(cpu_tlbstate.loaded_mm); + switch_mm_irqs_off(NULL, mm, current); + return state; +} + +static inline void unuse_temporary_mm(temporary_mm_state_t prev) +{ + lockdep_assert_irqs_disabled(); + switch_mm_irqs_off(NULL, prev.prev, current); +} + #endif /* _ASM_X86_MMU_CONTEXT_H */ -- 2.17.1