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[209.132.180.67]) by mx.google.com with ESMTP id j5si33825466pgq.82.2019.01.29.01.30.19; Tue, 29 Jan 2019 01:30:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727065AbfA2JaH (ORCPT + 99 others); Tue, 29 Jan 2019 04:30:07 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:44474 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725298AbfA2JaG (ORCPT ); Tue, 29 Jan 2019 04:30:06 -0500 X-UUID: adc0166cf5a74512bb7db5198f21d048-20190129 X-UUID: adc0166cf5a74512bb7db5198f21d048-20190129 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 667881208; Tue, 29 Jan 2019 17:29:57 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 29 Jan 2019 17:29:55 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 29 Jan 2019 17:29:50 +0800 Message-ID: <1548754190.11055.7.camel@mtksdaap41> Subject: Re: [PATCH 04/10] soc: mediatek: clear the event in cmdq initial flow From: CK Hu To: Bibby Hsieh CC: Jassi Brar , Matthias Brugger , Rob Herring , Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , "Philipp Zabel" , Nicolas Boichat , "YT Shen" , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , , , Frederic Chen Date: Tue, 29 Jan 2019 17:29:50 +0800 In-Reply-To: <1548747128-60136-5-git-send-email-bibby.hsieh@mediatek.com> References: <1548747128-60136-1-git-send-email-bibby.hsieh@mediatek.com> <1548747128-60136-5-git-send-email-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bibby: On Tue, 2019-01-29 at 15:32 +0800, Bibby Hsieh wrote: > GCE hardware stored event information in own internal sysram, > if the initial value in those sysram is not zero value > it will cause a situation that gce can wait the event immediately > after client ask gce to wait event but not really trigger the > corresponding hardware. > > In order to make sure that the wait event function is > exactly correct, we need to clear the sysram value in > cmdq initial flow. If MT8173 has the same problem, add a fix tag. Regards, CK > > Signed-off-by: Bibby Hsieh > --- > drivers/mailbox/mtk-cmdq-mailbox.c | 5 +++++ > include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++ > include/linux/soc/mediatek/mtk-cmdq.h | 3 --- > 3 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c > index f6174ca..2b5febd 100644 > --- a/drivers/mailbox/mtk-cmdq-mailbox.c > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c > @@ -33,6 +33,7 @@ > #define CMDQ_THR_END_ADDR 0x24 > #define CMDQ_THR_WAIT_TOKEN 0x30 > #define CMDQ_THR_PRIORITY 0x40 > +#define CMDQ_SYNC_TOKEN_UPDATE 0x68 > > #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 > #define CMDQ_THR_ENABLED 0x1 > @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) > > static void cmdq_init(struct cmdq *cmdq) > { > + int i; > + > WARN_ON(clk_enable(cmdq->clock) < 0); > writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); > + for (i = 0; i <= CMDQ_MAX_EVENT; i++) > + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); > clk_disable(cmdq->clock); > } > > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h > index ccb7342..911475da 100644 > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h > @@ -19,6 +19,8 @@ > #define CMDQ_WFE_UPDATE BIT(31) > #define CMDQ_WFE_WAIT BIT(15) > #define CMDQ_WFE_WAIT_VALUE 0x1 > +/** cmdq event maximum */ > +#define CMDQ_MAX_EVENT 0x3ff > > /* > * CMDQ_CODE_MASK: > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h > index 54ade13..4e88999 100644 > --- a/include/linux/soc/mediatek/mtk-cmdq.h > +++ b/include/linux/soc/mediatek/mtk-cmdq.h > @@ -13,9 +13,6 @@ > > #define CMDQ_NO_TIMEOUT 0xffffffffu > > -/** cmdq event maximum */ > -#define CMDQ_MAX_EVENT 0x3ff > - > struct cmdq_pkt; > > struct cmdq_client {