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[209.132.180.67]) by mx.google.com with ESMTP id b131si35056077pga.394.2019.01.29.05.22.18; Tue, 29 Jan 2019 05:22:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20150623.gappssmtp.com header.s=20150623 header.b=tGImw29C; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727077AbfA2NWN (ORCPT + 99 others); Tue, 29 Jan 2019 08:22:13 -0500 Received: from mail-io1-f67.google.com ([209.85.166.67]:34582 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726383AbfA2NWM (ORCPT ); Tue, 29 Jan 2019 08:22:12 -0500 Received: by mail-io1-f67.google.com with SMTP id b16so16309034ior.1 for ; Tue, 29 Jan 2019 05:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=wIWaIsd4IeVKGOT8ZDYtQy2OZmbN9N7gWb6nl2/X1VM=; b=tGImw29C2M+KMBY5gUuCCc0gudm2/UI05RC+KTfwOSAiqJbUJnlEHFSdM6NGci/AEU 2dX0IpY4mmHk/ruN2hAYDGz7rbYppooKfiKlAbN/xfoQYr2e+dzJX1nS1qAIGHPQJvfo SDoBuX9c/NRj12n9Vj/Z4oVRdWfx/hnndsxEAaVau8nhtPU0NTEBviVRUTfe7u79cnOy i0iQ70Rr3pw9vagjmXOmUY1UL9EThpdxnSjNOfB4jEPOHWm707P6c5wGIZRRNfiW15Bh dOcvMOjDnStTPUUxbOefFFS/Dq1k/8Sh+HQVeul4RS/AbewaIt0ZXcWSRUldBCmsW89S UvXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=wIWaIsd4IeVKGOT8ZDYtQy2OZmbN9N7gWb6nl2/X1VM=; b=JVp0gEJVHzeegpwefUNZo0c7pTbgDETUOk7OsuWG/s0cxtnc9/7o0ojvujZWs2IleZ RFO6H9REXRDHNuik6JIjK+bBFPclkSh4w+BqQPNbz36aK8YxHwQv4/z/NT9GzWCHYoLZ okqiq5vKxW5MKEe6+3JO7Un5Eexj7LiooO9kMNScGvQ82VHvTavtNB+ahQG/JJ6pRtdB nOX3yEyBXsGMEFFnURSdIjKHlUcZIoh4wsOZ/EeM6k5auSUNnJlDpKLE8YtPAbHcJdgu d+O8c/pejejT8K//LNJCFIsBoloDfL2Ce3cGtf5gddeJrIEhdvqlBJf/lLjW+yEh47wl Fugw== X-Gm-Message-State: AHQUAualf4QQEveg/UhaCLnlntVQ1Dj5gRfiavt7d8VyYawav1zE+4jd 6tA4F210F87wywJhUCo9zkEit/kUgSV5vxzVZHsW9g== X-Received: by 2002:a5d:928b:: with SMTP id s11mr16387362iom.111.1548768131091; Tue, 29 Jan 2019 05:22:11 -0800 (PST) MIME-Version: 1.0 References: <20190118134244.22253-1-brgl@bgdev.pl> <20190118134244.22253-11-brgl@bgdev.pl> In-Reply-To: From: Bartosz Golaszewski Date: Tue, 29 Jan 2019 14:22:00 +0100 Message-ID: Subject: Re: [PATCH 10/13] gpio: max77650: add GPIO support To: Linus Walleij Cc: Brian Masney , Rob Herring , Mark Rutland , Dmitry Torokhov , Jacek Anaszewski , Pavel Machek , Lee Jones , Sebastian Reichel , Liam Girdwood , Mark Brown , Greg Kroah-Hartman , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Input , Linux LED Subsystem , Linux PM list , Bartosz Golaszewski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org wt., 29 sty 2019 o 12:00 Bartosz Golaszewski napisa=C5=82(a= ): > > czw., 24 sty 2019 o 11:30 Linus Walleij napisa= =C5=82(a): > > > > On Mon, Jan 21, 2019 at 6:07 PM Bartosz Golaszewski wro= te: > > > > > Thank you for your review. While I think you're right about the issue > > > being present in this driver, I'm not sure it's really a problem. Do > > > we actually require every gpio-controller to also be a stand-alone > > > interrupt-controller? > > > > Absolutely not :D > > > > Just GPIO is fine. > > > > > The binding document for the GPIO module doesn't > > > mention this - it only requires the gpio-controller property. Without > > > the "interrupt-controller" property dtc will bail-out if anyone uses > > > this node as the interrupt parent. > > > > > > If I'm wrong and we do require it, then I think we need to update > > > Documentation/devicetree/bindings/gpio/gpio.txt. > > > > What is weird is if a driver with DT bindings not mentioning IRQ > > and only probing from DT start implementing IRQ support, that > > becomes quite inconsistent. So then max77650_gpio_to_irq() > > should just return -ENOTSUPP > > or something for now, then it's fine. > > > > I don't see it as weird at all. I see the need to define the register > and interrupt resources in DT for SoC peripherals becaue SoCs often > reuse IPs. But in the case of a self-contained i2c PMIC - the modules > such as GPIO are tightly coupled with the core functionality. In the > case of this device for example: there isn't even a separate set of > mask/status registers for GPIO interrupts. > > Most mfd devices setup the resources in a hard-coded manner. > > > We can add the (complicated) IRQ handling later. > > > > I am trying to eat my own dogfood here, I was sweating all > > last night trying to implement a hierarchical IRQ controller. > > There is no running away from that now. :/ > > > > Apparently doing hierarchical IRQs demand that all irq > > controllers up to the top-level SoC IRQ controller support > > hierarchical interrupts using the v2 version of the irqdomain > > API, and currently it seems like the ARM > > GIC seems like the only top level IRQ controller that can > > do that. > > > > Yep, and for that reason I can't use the regmap irq_chip abstraction > for now because it doesn't implement support for hierarchical > interrupts either. > > How about the cascaded gpiochip irq_chip? > > Best regards, > Bartosz Nah that won't work either without a proper hierarchy... In that case, let's leave out the irq support for now. I'll send v2. Bart